bench51srcinstructions.rs
| 1 | #[repr(u8)] |
| 2 | pub enum Instruction { |
| 3 | MOV_RI = 0x01, |
| 4 | MOV_RR = 0x08, |
| 5 | ADD = 0x02, |
| 6 | SUB = 0x03, |
| 7 | JMP = 0x04, |
| 8 | JZ = 0x05, |
| 9 | JNZ = 0x06, |
| 10 | CMP_RI = 0x07, |
| 11 | CMP_RR = 0x09, |
| 12 | HLT = 0xFF, |
| 13 | } |
| 14 | |
| 15 | impl Instruction { |
| 16 | pub fn opcode_name(op: u8) -> &'static str{ |
| 17 | match op { |
| 18 | 0x01 | 0x08 => "MOV", |
| 19 | 0x02 => "ADD", |
| 20 | 0x03 => "SUB", |
| 21 | 0x04 => "JMP", |
| 22 | 0x05 => "JZ", |
| 23 | 0x06 => "JNZ", |
| 24 | 0x07 | 0x09 => "CMP", |
| 25 | 0xFF => "HLT", |
| 26 | _ => "???", |
| 27 | } |
| 28 | } |
| 29 | } |