bench51srcinstructions.rs
| 1 | #[repr(u8)] |
| 2 | #[allow(non_camel_case_types)] |
| 3 | pub enum Instruction { |
| 4 | MOV_RI = 0x01, |
| 5 | MOV_RR = 0x08, |
| 6 | ADD_RR = 0x02, |
| 7 | ADD_RI = 0x0A, |
| 8 | SUB_RR = 0x03, |
| 9 | SUB_RI = 0x0B, |
| 10 | JMP = 0x04, |
| 11 | JZ = 0x05, |
| 12 | JNZ = 0x06, |
| 13 | CMP_RI = 0x07, |
| 14 | CMP_RR = 0x09, |
| 15 | MUL = 0x0C, |
| 16 | DIV = 0x0D, |
| 17 | CALL = 0x0E, |
| 18 | RET = 0x0F, |
| 19 | SYS = 0x10, |
| 20 | HLT = 0xFF, |
| 21 | } |
| 22 | |
| 23 | impl Instruction { |
| 24 | pub fn opcode_name(op: u8) -> &'static str { |
| 25 | match op { |
| 26 | 0x01 | 0x08 => "MOV", |
| 27 | 0x02 | 0x0A => "ADD", |
| 28 | 0x03 | 0x0B => "SUB", |
| 29 | 0x04 => "JMP", |
| 30 | 0x05 => "JZ", |
| 31 | 0x06 => "JNZ", |
| 32 | 0x07 | 0x09 => "CMP", |
| 33 | 0x0C => "MUL", |
| 34 | 0x0D => "DIV", |
| 35 | 0x0E => "CALL", |
| 36 | 0x0F => "RET", |
| 37 | 0x10 => "SYS", |
| 38 | 0xFF => "HLT", |
| 39 | |
| 40 | _ => "???", |
| 41 | } |
| 42 | } |
| 43 | } |