Krolyxon
Commit 1d55752

Branches

Tags

Refs →

orion-rf.piolibdepsesp32-s3-n16r8U8g2srcclibu8x8_d_ssd1327.c

1043 lines · 36.7 KB · C

Raw Blame History Download
1/*
2
3 u8x8_d_ssd1327.c
4
5 Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
6
7 Copyright (c) 2016, olikraus@gmail.com
8 All rights reserved.
9
10 Redistribution and use in source and binary forms, with or without modification,
11 are permitted provided that the following conditions are met:
12
13 * Redistributions of source code must retain the above copyright notice, this list
14 of conditions and the following disclaimer.
15
16 * Redistributions in binary form must reproduce the above copyright notice, this
17 list of conditions and the following disclaimer in the documentation and/or other
18 materials provided with the distribution.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
34*/
35
36
37#include "u8x8.h"
38
39
40static const uint8_t u8x8_d_ssd1327_96x96_powersave0_seq[] = {
41 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
42 U8X8_C(0x0af), /* display on */
43 U8X8_END_TRANSFER(), /* disable chip */
44 U8X8_END() /* end of sequence */
45};
46
47static const uint8_t u8x8_d_ssd1327_96x96_powersave1_seq[] = {
48 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
49 U8X8_C(0x0ae), /* display off */
50 U8X8_END_TRANSFER(), /* disable chip */
51 U8X8_END() /* end of sequence */
52};
53
54
55static const uint8_t u8x8_d_ssd1327_seeed_96x96_flip0_seq[] = {
56 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
57 U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
58 U8X8_CA(0x0a0, 0x051), /* remap configuration */
59 U8X8_END_TRANSFER(), /* disable chip */
60 U8X8_END() /* end of sequence */
61};
62
63static const uint8_t u8x8_d_ssd1327_seeed_96x96_flip1_seq[] = {
64 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
65 U8X8_CA(0x0a2, 0x060), /* display offset, shift mapping ram counter */
66 U8X8_CA(0x0a0, 0x042), /* remap configuration */
67 U8X8_END_TRANSFER(), /* disable chip */
68 U8X8_END() /* end of sequence */
69};
70
71
72static const uint8_t u8x8_d_ssd1327_winstar_96x64_flip0_seq[] = {
73 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
74 U8X8_CA(0x0a0, 0x042), /* remap configuration */
75 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
76 U8X8_END_TRANSFER(), /* disable chip */
77 U8X8_END() /* end of sequence */
78};
79
80static const uint8_t u8x8_d_ssd1327_winstar_96x64_flip1_seq[] = {
81 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
82 U8X8_CA(0x0a0, 0x051), /* remap configuration */
83 U8X8_CA(0x0a2, 0x040), /* display offset, shift mapping ram counter */
84 U8X8_END_TRANSFER(), /* disable chip */
85 U8X8_END() /* end of sequence */
86};
87
88/*
89 input:
90 one tile (8 Bytes)
91 output:
92 Tile for ssd1327 (32 Bytes)
93*/
94
95static uint8_t u8x8_ssd1327_8to32_dest_buf[32];
96
97static uint8_t *u8x8_ssd1327_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)
98{
99 uint8_t v;
100 uint8_t a,b;
101 uint8_t i, j;
102 uint8_t *dest;
103
104 for( j = 0; j < 4; j++ )
105 {
106 dest = u8x8_ssd1327_8to32_dest_buf;
107 dest += j;
108 a =*ptr;
109 ptr++;
110 b = *ptr;
111 ptr++;
112 for( i = 0; i < 8; i++ )
113 {
114 v = 0;
115 if ( a&1 ) v |= 0xf0;
116 if ( b&1 ) v |= 0x0f;
117 *dest = v;
118 dest+=4;
119 a >>= 1;
120 b >>= 1;
121 }
122 }
123
124 return u8x8_ssd1327_8to32_dest_buf;
125}
126
127
128
129
130static uint8_t u8x8_d_ssd1327_96x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
131{
132 uint8_t x, y, c;
133 uint8_t *ptr;
134 switch(msg)
135 {
136 /* handled by the calling function
137 case U8X8_MSG_DISPLAY_SETUP_MEMORY:
138 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_96x96_display_info);
139 break;
140 */
141 /* handled by the calling function
142 case U8X8_MSG_DISPLAY_INIT:
143 u8x8_d_helper_display_init(u8x8);
144 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_init_seq);
145 break;
146 */
147 case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
148 if ( arg_int == 0 )
149 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_powersave0_seq);
150 else
151 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_powersave1_seq);
152 break;
153#ifdef U8X8_WITH_SET_CONTRAST
154 case U8X8_MSG_DISPLAY_SET_CONTRAST:
155 u8x8_cad_StartTransfer(u8x8);
156 u8x8_cad_SendCmd(u8x8, 0x081 );
157 u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1327 has range from 0 to 255 */
158 u8x8_cad_EndTransfer(u8x8);
159 break;
160#endif
161 case U8X8_MSG_DISPLAY_DRAW_TILE:
162 u8x8_cad_StartTransfer(u8x8);
163 x = ((u8x8_tile_t *)arg_ptr)->x_pos;
164 x *= 4;
165 x+=u8x8->x_offset/2;
166
167 y = (((u8x8_tile_t *)arg_ptr)->y_pos);
168 y *= 8;
169
170 u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address, moved out of the loop (issue 302) */
171 u8x8_cad_SendArg(u8x8, y);
172 u8x8_cad_SendArg(u8x8, y+7);
173
174
175 do
176 {
177 c = ((u8x8_tile_t *)arg_ptr)->cnt;
178 ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;
179
180 do
181 {
182 u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */
183 u8x8_cad_SendArg(u8x8, x ); /* start */
184 u8x8_cad_SendArg(u8x8, x+3 ); /* end */
185
186
187 u8x8_cad_SendData(u8x8, 32, u8x8_ssd1327_8to32(u8x8, ptr));
188 ptr += 8;
189 x += 4;
190 c--;
191 } while( c > 0 );
192
193 //x += 4;
194 arg_int--;
195 } while( arg_int > 0 );
196
197 u8x8_cad_EndTransfer(u8x8);
198 break;
199 default:
200 return 0;
201 }
202 return 1;
203}
204
205/*=============================================*/
206/*
207 Winstar WEA009664B 96x64 OLED Display, 1.1 inch OLED
208 https://www.winstar.com.tw/products/oled-module/graphic-oled-display/96x64-oled.html
209
210 https://github.com/olikraus/u8g2/issues/1050
211*/
212
213static const u8x8_display_info_t u8x8_ssd1327_winstar_96x64_display_info =
214{
215 /* chip_enable_level = */ 0,
216 /* chip_disable_level = */ 1,
217
218 /* post_chip_enable_wait_ns = */ 20,
219 /* pre_chip_disable_wait_ns = */ 10,
220 /* reset_pulse_width_ms = */ 100,
221 /* post_reset_wait_ms = */ 100, /**/
222 /* sda_setup_time_ns = */ 100, /* */
223 /* sck_pulse_width_ns = */ 100, /* */
224 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
225 /* spi_mode = */ 0, /* active high, rising edge */
226 /* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow */
227 /* data_setup_time_ns = */ 40,
228 /* write_pulse_width_ns = */ 60,
229 /* tile_width = */ 12,
230 /* tile_height = */ 8,
231 /* default_x_offset = */ 16, /* changed to 16, issue 1050 */
232 /* flipmode_x_offset = */ 16, /* changed to 16, issue 1050 */
233 /* pixel_width = */ 96,
234 /* pixel_height = */ 64
235};
236
237/*
238 Write_Cmd(0xAE); //Set Display Off OK
239 Write_Cmd(0x81); //Contrast Level OK
240 Write_Cmd(0xdF); // VALUE WRONG????
241 Write_Cmd(0xD9); //Pre-charge Period
242 Write_Cmd(0x00);
243 Write_Cmd(0xA0); //Set Re-map OK
244 Write_Cmd(0x42); //Default Setting OK
245 Write_Cmd(0xA1); //Set Display Start Line OK
246 Write_Cmd(0x00); OK
247 Write_Cmd(0xA2); //Set Display Offset OK
248 Write_Cmd(0x00); OK
249 Write_Cmd(0xA4); //Set Display Mode OK
250 Write_Cmd(0xA8); //Set Multiplex Ratio OK
251 Write_Cmd(0x63); //Multiplex OK
252 Write_Cmd(0xAB); //Set Function SelectionA OK
253 Write_Cmd(0x01); OK
254 Write_Cmd(0xB1); //Set Phase Length OK
255 Write_Cmd(0x47); OK
256 Write_Cmd(0xB3); //Set Display Clock Divide Ratio/Oscillator Frequency OK
257 Write_Cmd(0x00); OK
258 Write_Cmd(0xBC); //Set Prechange Voltage OK
259 Write_Cmd(0x07); OK
260 Write_Cmd(0xBE); //Set VCOMH Voltage OK
261 Write_Cmd(0x07); OK
262 Write_Cmd(0xB6); //Set Second Pre-charge period OK
263 Write_Cmd(0x04); OK
264 Write_Cmd(0xD5); //Set Function selection B OK
265 Write_Cmd(0x62); OK
266 Write_Cmd(0xAF); //Set Display On
267
268*/
269
270static const uint8_t u8x8_d_ssd1327_winstar_96x64_init_seq[] = {
271
272 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
273
274 U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
275 U8X8_C(0x0ae), /* display off */
276
277 U8X8_CA(0x0d9, 0x000), /* Pre-charge Period ??? */
278
279 U8X8_CA(0x0a0, 0x042), /* remap configuration */
280 U8X8_CA(0x0a1, 0x000), /* display start line */
281 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
282
283 U8X8_CA(0x0a8, 0x063), /* multiplex ratio: 63* 1/64 duty */ /* changed to hex, issue 1050 */
284
285 U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
286 U8X8_CA(0x081, 0x053), /* contrast, brightness, 0..128 */
287
288 U8X8_CA(0x0b1, 0x047), /* phase length */
289 //U8X8_CA(0x0b3, 0x001), /* set display clock divide ratio/oscillator frequency */
290 U8X8_CA(0x0b3, 0x000), /* set display clock divide ratio/oscillator frequency */
291
292 U8X8_C(0x0b9), /* use linear lookup table */
293
294 U8X8_CA(0x0bc, 0x007), /* pre-charge voltage level */
295 U8X8_CA(0x0be, 0x007), /* VCOMH voltage */
296 U8X8_CA(0x0b6, 0x004), /* second precharge */
297 U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
298
299 U8X8_C(0x0a4), /* normal display mode */
300
301 U8X8_END_TRANSFER(), /* disable chip */
302 U8X8_END() /* end of sequence */
303};
304
305uint8_t u8x8_d_ssd1327_ws_96x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
306{
307 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
308 return 1;
309 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
310 {
311 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_winstar_96x64_display_info);
312 return 1;
313 }
314 else if ( msg == U8X8_MSG_DISPLAY_INIT )
315 {
316 u8x8_d_helper_display_init(u8x8);
317 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_init_seq);
318 return 1;
319 }
320 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
321 {
322 if ( arg_int == 0 )
323 {
324 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_flip0_seq);
325 u8x8->x_offset = u8x8->display_info->default_x_offset;
326 }
327 else
328 {
329 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_flip1_seq);
330 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
331 }
332 return 1;
333 }
334 return 0;
335}
336
337
338/*=============================================*/
339/* Seeedstudio Grove OLED 96x96 */
340
341static const u8x8_display_info_t u8x8_ssd1327_96x96_display_info =
342{
343 /* chip_enable_level = */ 0,
344 /* chip_disable_level = */ 1,
345
346 /* post_chip_enable_wait_ns = */ 20,
347 /* pre_chip_disable_wait_ns = */ 10,
348 /* reset_pulse_width_ms = */ 100,
349 /* post_reset_wait_ms = */ 100, /**/
350 /* sda_setup_time_ns = */ 100, /* */
351 /* sck_pulse_width_ns = */ 100, /* */
352 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
353 /* spi_mode = */ 0, /* active high, rising edge */
354 /* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow */
355 /* data_setup_time_ns = */ 40,
356 /* write_pulse_width_ns = */ 60,
357 /* tile_width = */ 12,
358 /* tile_height = */ 12,
359 /* default_x_offset = */ 16,
360 /* flipmode_x_offset = */ 16,
361 /* pixel_width = */ 96,
362 /* pixel_height = */ 96
363};
364
365/* https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */
366/* http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */
367/* values from u8glib */
368/*
369 Re-map setting in Graphic Display Data RAM, command 0x0a0
370 Bit 0: Column Address Re-map
371 Bit 1: Nibble Re-map
372 Bit 2: Horizontal/Vertical Address Increment
373 Bit 3: Not used, must be 0
374
375 Bit 4: COM Re-map
376 Bit 5: Not used, must be 0
377 Bit 6: COM Split Odd Even
378 Bit 7: Not used, must be 0
379*/
380
381
382static const uint8_t u8x8_d_ssd1327_96x96_init_seq[] = {
383
384 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
385
386 U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
387 U8X8_C(0x0ae), /* display off */
388 //U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
389 U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x05f * 1/64 duty */
390 U8X8_CA(0x0a1, 0x000), /* display start line */
391 //U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
392
393 U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
394 U8X8_CA(0x0a0, 0x051), /* remap configuration */
395
396
397 U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
398 //U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
399 U8X8_CA(0x081, 0x053), /* contrast, brightness, 0..128 */
400 //U8X8_CA(0x0b1, 0x055), /* phase length */
401 U8X8_CA(0x0b1, 0x051), /* phase length */
402 //U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
403 U8X8_CA(0x0b3, 0x001), /* set display clock divide ratio/oscillator frequency */
404
405 //? U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
406 //? U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
407
408 U8X8_C(0x0b9), /* use linear lookup table */
409
410 //U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
411 U8X8_CA(0x0bc, 0x008), /* pre-charge voltage level */
412 //U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
413 U8X8_CA(0x0be, 0x007), /* VCOMH voltage */
414 U8X8_CA(0x0b6, 0x001), /* second precharge */
415 U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
416
417
418
419 U8X8_C(0x0a4), /* normal display mode */
420
421 U8X8_END_TRANSFER(), /* disable chip */
422 U8X8_END() /* end of sequence */
423};
424
425
426
427
428uint8_t u8x8_d_ssd1327_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
429{
430 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
431 return 1;
432 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
433 {
434 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_96x96_display_info);
435 return 1;
436 }
437 else if ( msg == U8X8_MSG_DISPLAY_INIT )
438 {
439 u8x8_d_helper_display_init(u8x8);
440 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_init_seq);
441 return 1;
442 }
443 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
444 {
445 if ( arg_int == 0 )
446 {
447 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_seeed_96x96_flip0_seq);
448 u8x8->x_offset = u8x8->display_info->default_x_offset;
449 }
450 else
451 {
452 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_seeed_96x96_flip1_seq);
453 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
454 }
455 return 1;
456 }
457 return 0;
458}
459
460/*=============================================*/
461/* EA W128128 round OLED 128x128 */
462/* issue #641 */
463/* https://www.lcd-module.de/fileadmin/eng/pdf/grafik/W128128-XR.pdf */
464
465static const u8x8_display_info_t u8x8_ssd1327_ea_w128128_display_info =
466{
467 /* chip_enable_level = */ 0,
468 /* chip_disable_level = */ 1,
469
470 /* post_chip_enable_wait_ns = */ 20,
471 /* pre_chip_disable_wait_ns = */ 10,
472 /* reset_pulse_width_ms = */ 100,
473 /* post_reset_wait_ms = */ 100, /**/
474 /* sda_setup_time_ns = */ 100, /* */
475 /* sck_pulse_width_ns = */ 100, /* */
476 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
477 /* spi_mode = */ 0, /* active high, rising edge */
478 /* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow */
479 /* data_setup_time_ns = */ 40,
480 /* write_pulse_width_ns = */ 60,
481 /* tile_width = */ 16,
482 /* tile_height = */ 16,
483 /* default_x_offset = */ 0,
484 /* flipmode_x_offset = */ 0,
485 /* pixel_width = */ 128,
486 /* pixel_height = */ 128
487};
488
489/* this is a copy of the init sequence for the seeed 96x96 oled */
490static const uint8_t u8x8_d_ssd1327_ea_w128128_init_seq[] = {
491
492 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
493
494 U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
495 U8X8_C(0x0ae), /* display off */
496 //U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
497 U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x05f * 1/64 duty */
498 U8X8_CA(0x0a1, 0x000), /* display start line */
499 //U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
500
501 U8X8_CA(0x0a2, 0x010), /* display offset, shift mapping ram counter */
502 U8X8_CA(0x0a0, 0x051), /* remap configuration */
503
504
505 U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
506 //U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
507 U8X8_CA(0x081, 0x053), /* contrast, brightness, 0..128 */
508 //U8X8_CA(0x0b1, 0x055), /* phase length */
509 U8X8_CA(0x0b1, 0x051), /* phase length */
510 //U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
511 U8X8_CA(0x0b3, 0x001), /* set display clock divide ratio/oscillator frequency */
512
513 //? U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
514 //? U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
515
516 U8X8_C(0x0b9), /* use linear lookup table */
517
518 //U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
519 U8X8_CA(0x0bc, 0x008), /* pre-charge voltage level */
520 //U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
521 U8X8_CA(0x0be, 0x007), /* VCOMH voltage */
522 U8X8_CA(0x0b6, 0x001), /* second precharge */
523 U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
524
525 U8X8_C(0x0a4), /* normal display mode */
526
527 U8X8_END_TRANSFER(), /* disable chip */
528 U8X8_END() /* end of sequence */
529};
530
531
532
533static const uint8_t u8x8_d_ssd1327_ea_w128128_flip0_seq[] = {
534 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
535 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
536 U8X8_CA(0x0a0, 0x051), /* remap configuration */
537 U8X8_END_TRANSFER(), /* disable chip */
538 U8X8_END() /* end of sequence */
539};
540
541static const uint8_t u8x8_d_ssd1327_ea_w128128_flip1_seq[] = {
542 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
543 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
544 U8X8_CA(0x0a0, 0x042), /* remap configuration */
545 U8X8_END_TRANSFER(), /* disable chip */
546 U8X8_END() /* end of sequence */
547};
548
549uint8_t u8x8_d_ssd1327_ea_w128128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
550{
551 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
552 return 1;
553 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
554 {
555 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_ea_w128128_display_info);
556 return 1;
557 }
558 else if ( msg == U8X8_MSG_DISPLAY_INIT )
559 {
560 u8x8_d_helper_display_init(u8x8);
561 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_init_seq);
562 return 1;
563 }
564 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
565 {
566 if ( arg_int == 0 )
567 {
568 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip0_seq);
569 u8x8->x_offset = u8x8->display_info->default_x_offset;
570 }
571 else
572 {
573 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip1_seq);
574 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
575 }
576 return 1;
577 }
578 return 0;
579}
580
581/*=============================================*/
582/* MIDAS MCOT128128C1V-YM 128x128 Module */
583
584
585static const u8x8_display_info_t u8x8_ssd1327_128x128_display_info =
586{
587 /* chip_enable_level = */ 0,
588 /* chip_disable_level = */ 1,
589
590 /* post_chip_enable_wait_ns = */ 20,
591 /* pre_chip_disable_wait_ns = */ 10,
592 /* reset_pulse_width_ms = */ 100,
593 /* post_reset_wait_ms = */ 100, /**/
594 /* sda_setup_time_ns = */ 100, /* */
595 /* sck_pulse_width_ns = */ 100, /* */
596 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
597 /* spi_mode = */ 0, /* active high, rising edge */
598 /* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow, Update 9 Aug 2019: The OLED from aliexpress supports 400kHz */
599 /* data_setup_time_ns = */ 40,
600 /* write_pulse_width_ns = */ 60,
601 /* tile_width = */ 16,
602 /* tile_height = */ 16,
603 /* default_x_offset = */ 0,
604 /* flipmode_x_offset = */ 0,
605 /* pixel_width = */ 128,
606 /* pixel_height = */ 128
607};
608
609/* https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */
610/* http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */
611/* values from u8glib */
612/*
613 Re-map setting in Graphic Display Data RAM, command 0x0a0
614 Bit 0: Column Address Re-map
615 Bit 1: Nibble Re-map
616 Bit 2: Horizontal/Vertical Address Increment
617 Bit 3: Not used, must be 0
618
619 Bit 4: COM Re-map
620 Bit 5: Not used, must be 0
621 Bit 6: COM Split Odd Even
622 Bit 7: Not used, must be 0
623*/
624
625
626static const uint8_t u8x8_d_ssd1327_128x128_init_seq[] = {
627
628 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
629
630
631 U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
632 U8X8_C(0x0ae), /* display off */
633 //U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
634 //U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x05f * 1/64 duty */
635 U8X8_CA(0x0a8, 0x07f), /* multiplex ratio: 0x05f * 1/128duty */
636 U8X8_CA(0x0a1, 0x000), /* display start line */
637 //U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
638
639 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
640 U8X8_CA(0x0a0, 0x051), /* remap configuration */
641
642
643 U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
644 //U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
645 U8X8_CA(0x081, 0x053), /* contrast, brightness, 0..128 */
646 //U8X8_CA(0x0b1, 0x055), /* phase length */
647 U8X8_CA(0x0b1, 0x051), /* phase length */
648 //U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
649 U8X8_CA(0x0b3, 0x001), /* set display clock divide ratio/oscillator frequency */
650
651 //? U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
652 //? U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
653
654 U8X8_C(0x0b9), /* use linear lookup table */
655
656 //U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
657 U8X8_CA(0x0bc, 0x008), /* pre-charge voltage level */
658 //U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
659 U8X8_CA(0x0be, 0x007), /* VCOMH voltage */
660 U8X8_CA(0x0b6, 0x001), /* second precharge */
661 U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
662
663
664
665 U8X8_C(0x0a4), /* normal display mode */
666
667 U8X8_END_TRANSFER(), /* disable chip */
668 U8X8_END() /* end of sequence */
669};
670
671
672static const uint8_t u8x8_d_ssd1327_128x128_flip0_seq[] = {
673 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
674 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
675 U8X8_CA(0x0a0, 0x051), /* remap configuration */
676 U8X8_END_TRANSFER(), /* disable chip */
677 U8X8_END() /* end of sequence */
678};
679
680static const uint8_t u8x8_d_ssd1327_128x128_flip1_seq[] = {
681 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
682 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
683 U8X8_CA(0x0a0, 0x042), /* remap configuration */
684 U8X8_END_TRANSFER(), /* disable chip */
685 U8X8_END() /* end of sequence */
686};
687
688
689uint8_t u8x8_d_ssd1327_midas_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
690{
691 /* call the 96x96 procedure at the moment */
692 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
693 return 1;
694 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
695 {
696 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_128x128_display_info);
697 return 1;
698 }
699 else if ( msg == U8X8_MSG_DISPLAY_INIT )
700 {
701 u8x8_d_helper_display_init(u8x8);
702 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_init_seq);
703 return 1;
704 }
705 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
706 {
707 if ( arg_int == 0 )
708 {
709 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_flip0_seq);
710 u8x8->x_offset = u8x8->display_info->default_x_offset;
711 }
712 else
713 {
714 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_flip1_seq);
715 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
716 }
717 return 1;
718 }
719 return 0;
720}
721
722/*=============================================*/
723/*
724
725 ZJY-M150 128x128
726
727 https://aliexpress.com/item/1005003784174529.html
728 https://github.com/olikraus/u8g2/issues/1960
729
730 Mostly like the MIDAS version, but requires the GPIO enabled.
731
732*/
733
734static const uint8_t u8x8_d_ssd1327_zjy_128x128_init_seq[] = {
735
736 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
737
738
739 U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
740 U8X8_C(0x0ae), /* display off */
741 //U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
742 //U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x05f * 1/64 duty */
743 U8X8_CA(0x0a8, 0x07f), /* multiplex ratio: 0x05f * 1/128duty */
744 U8X8_CA(0x0a1, 0x000), /* display start line */
745 //U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
746
747 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
748 U8X8_CA(0x0a0, 0x051), /* remap configuration */
749
750
751 U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
752 //U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
753 U8X8_CA(0x081, 0x053), /* contrast, brightness, 0..128 */
754 //U8X8_CA(0x0b1, 0x055), /* phase length */
755 U8X8_CA(0x0b1, 0x051), /* phase length */
756 //U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
757 U8X8_CA(0x0b3, 0x001), /* set display clock divide ratio/oscillator frequency */
758
759 //? U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
760 //? U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
761
762 U8X8_C(0x0b9), /* use linear lookup table */
763
764 //U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
765 U8X8_CA(0x0bc, 0x008), /* pre-charge voltage level */
766 //U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
767 U8X8_CA(0x0be, 0x007), /* VCOMH voltage */
768
769 U8X8_CA(0x0b6, 0x001), /* second precharge */
770 U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
771
772 U8X8_CA(0x0b5, 0x003), /* Enable GPIO, issue 1960 */
773
774
775 U8X8_C(0x0a4), /* normal display mode */
776
777 U8X8_END_TRANSFER(), /* disable chip */
778 U8X8_END() /* end of sequence */
779};
780
781uint8_t u8x8_d_ssd1327_zjy_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
782{
783 /* call the 96x96 procedure at the moment */
784 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
785 return 1;
786 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
787 {
788 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_128x128_display_info);
789 return 1;
790 }
791 else if ( msg == U8X8_MSG_DISPLAY_INIT )
792 {
793 u8x8_d_helper_display_init(u8x8);
794 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_zjy_128x128_init_seq);
795 return 1;
796 }
797 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
798 {
799 if ( arg_int == 0 )
800 {
801 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_flip0_seq);
802 u8x8->x_offset = u8x8->display_info->default_x_offset;
803 }
804 else
805 {
806 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_flip1_seq);
807 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
808 }
809 return 1;
810 }
811 return 0;
812}
813
814/*=============================================*/
815/*
816 Waveshare 128x128 Module
817 https://www.waveshare.com/w/upload/8/80/1.5inch_OLED_Module_User_Manual_EN.pdf
818 https://github.com/olikraus/u8g2/issues/880
819
820 This is mostly a takeover of the EA display.
821*/
822
823/* https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */
824/* http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */
825/* values from u8glib */
826/*
827 Re-map setting in Graphic Display Data RAM, command 0x0a0
828 Bit 0: Column Address Re-map
829 Bit 1: Nibble Re-map
830 Bit 2: Horizontal/Vertical Address Increment
831 Bit 3: Not used, must be 0
832
833 Bit 4: COM Re-map
834 Bit 5: Not used, must be 0
835 Bit 6: COM Split Odd Even
836 Bit 7: Not used, must be 0
837*/
838
839/* takeover from https://github.com/olikraus/u8g2/issues/880 */
840static const uint8_t u8x8_d_ssd1327_ws_128x128_init_seq[] = {
841
842 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
843
844 U8X8_C(0x0ae), //--turn off oled panel
845 U8X8_CAA(0x015, 0x000, 0x07f), //set column address, start column 0, end column 127
846 U8X8_CAA(0x075, 0x000, 0x07f), //set row address, start row 0, end row 127
847 U8X8_CA(0x081, 0x080), //set contrast control
848 U8X8_CA(0x0a0, 0x051), //gment remap, 51
849 U8X8_CA(0x0a1, 0x000), //start line
850 U8X8_CA(0x0a2, 0x000), //display offset
851 U8X8_CAA(0x0a4, 0x0a8, 0x07f), //rmal display, set multiplex ratio
852 U8X8_CA(0x0b1, 0x0f1), //set phase leghth
853 U8X8_CA(0x0b3, 0x000), //set dclk, 80Hz:0xc1 90Hz:0xe1 100Hz:0x00 110Hz:0x30 120Hz:0x50 130Hz:0x70 01
854 U8X8_CA(0x0ab, 0x001), //
855 U8X8_CA(0x0b6, 0x00f), //set phase leghth
856 U8X8_CA(0x0be, 0x00f),
857 U8X8_CA(0x0bc, 0x008),
858 U8X8_CA(0x0d5, 0x062),
859 U8X8_CA(0x0fd, 0x012),
860
861 U8X8_END_TRANSFER(), /* disable chip */
862 U8X8_END() /* end of sequence */
863 };
864
865
866uint8_t u8x8_d_ssd1327_ws_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
867{
868 /* call the 96x96 procedure at the moment */
869 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
870 return 1;
871 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
872 {
873 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_ea_w128128_display_info);
874 return 1;
875 }
876 else if ( msg == U8X8_MSG_DISPLAY_INIT )
877 {
878 u8x8_d_helper_display_init(u8x8);
879 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ws_128x128_init_seq);
880 return 1;
881 }
882 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
883 {
884 if ( arg_int == 0 )
885 {
886 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip0_seq);
887 u8x8->x_offset = u8x8->display_info->default_x_offset;
888 }
889 else
890 {
891 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip1_seq);
892 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
893 }
894 return 1;
895 }
896 return 0;
897}
898
899
900
901
902/*=============================================*/
903/*
904Visonox VGM128096A4W10 128x96 COB
905https://github.com/olikraus/u8g2/files/4052919/M02289_VGM128096A4W10_Y02.pdf
906https://github.com/olikraus/u8g2/issues/1090
907*/
908
909
910static const u8x8_display_info_t u8x8_ssd1327_128x96_display_info =
911{
912 /* chip_enable_level = */ 0,
913 /* chip_disable_level = */ 1,
914
915 /* post_chip_enable_wait_ns = */ 20,
916 /* pre_chip_disable_wait_ns = */ 10,
917 /* reset_pulse_width_ms = */ 100,
918 /* post_reset_wait_ms = */ 100, /**/
919 /* sda_setup_time_ns = */ 100, /* */
920 /* sck_pulse_width_ns = */ 100, /* */
921 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
922 /* spi_mode = */ 0, /* active high, rising edge */
923 /* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow, Update 9 Aug 2019: The OLED from aliexpress supports 400kHz */
924 /* data_setup_time_ns = */ 40,
925 /* write_pulse_width_ns = */ 60,
926 /* tile_width = */ 16,
927 /* tile_height = */ 12,
928 /* default_x_offset = */ 0,
929 /* flipmode_x_offset = */ 0,
930 /* pixel_width = */ 128,
931 /* pixel_height = */ 96
932};
933
934/* https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */
935/* http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */
936/* values from u8glib */
937/*
938 Re-map setting in Graphic Display Data RAM, command 0x0a0
939 Bit 0: Column Address Re-map
940 Bit 1: Nibble Re-map
941 Bit 2: Horizontal/Vertical Address Increment
942 Bit 3: Not used, must be 0
943
944 Bit 4: COM Re-map
945 Bit 5: Not used, must be 0
946 Bit 6: COM Split Odd Even
947 Bit 7: Not used, must be 0
948*/
949
950/* init values from the Visionox datasheeet section 10.4 */
951
952static const uint8_t u8x8_d_ssd1327_128x96_init_seq[] = {
953
954 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
955
956
957 U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
958 U8X8_C(0x0ae), /* display off */
959 //U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
960 U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x05f * 1/64 duty */
961 //U8X8_CA(0x0a8, 0x07f), /* multiplex ratio: 0x05f * 1/128duty */
962 U8X8_CA(0x0a1, 0x000), /* display start line */
963 //U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
964
965 U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
966 U8X8_CA(0x0a0, 0x051), /* remap configuration */
967
968
969 U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
970 //U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
971 U8X8_CA(0x081, 0x0df), /* contrast, brightness, 0..128 (0xdf as per datasheet) */
972 U8X8_CA(0x0b1, 0x022), /* phase length */
973 U8X8_CA(0x0b3, 0x050), /* set display clock divide ratio/oscillator frequency */
974
975 //? U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
976 //? U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
977
978 U8X8_C(0x0b9), /* use linear lookup table */
979
980 U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
981 U8X8_CA(0x0be, 0x005), /* VCOMH voltage */
982 U8X8_CA(0x0b6, 0x00a), /* second precharge */
983 U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
984
985
986
987 U8X8_C(0x0a4), /* normal display mode */
988
989 U8X8_END_TRANSFER(), /* disable chip */
990 U8X8_END() /* end of sequence */
991};
992
993
994static const uint8_t u8x8_d_ssd1327_128x96_flip0_seq[] = {
995 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
996 U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
997 U8X8_CA(0x0a0, 0x051), /* remap configuration */
998 U8X8_END_TRANSFER(), /* disable chip */
999 U8X8_END() /* end of sequence */
1000};
1001
1002static const uint8_t u8x8_d_ssd1327_128x96_flip1_seq[] = {
1003 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
1004 U8X8_CA(0x0a2, 0x060), /* display offset, shift mapping ram counter */
1005 U8X8_CA(0x0a0, 0x042), /* remap configuration */
1006 U8X8_END_TRANSFER(), /* disable chip */
1007 U8X8_END() /* end of sequence */
1008};
1009
1010
1011uint8_t u8x8_d_ssd1327_visionox_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
1012{
1013 /* call the 96x96 procedure at the moment */
1014 if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
1015 return 1;
1016 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
1017 {
1018 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_128x96_display_info);
1019 return 1;
1020 }
1021 else if ( msg == U8X8_MSG_DISPLAY_INIT )
1022 {
1023 u8x8_d_helper_display_init(u8x8);
1024 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_init_seq);
1025 return 1;
1026 }
1027 else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
1028 {
1029 if ( arg_int == 0 )
1030 {
1031 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_flip0_seq);
1032 u8x8->x_offset = u8x8->display_info->default_x_offset;
1033 }
1034 else
1035 {
1036 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_flip1_seq);
1037 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
1038 }
1039 return 1;
1040 }
1041 return 0;
1042}
1043