Krolyxon
Commit 1d55752

Branches

Tags

Refs →

orion-rf.piolibdepsesp32-s3-n16r8U8g2srcclibu8x8_d_ssd1329.c

513 lines · 17.1 KB · C

Raw Blame History Download
1/*
2
3 u8x8_d_ssd1329.c
4
5 Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
6
7 Copyright (c) 2016, olikraus@gmail.com
8 All rights reserved.
9
10 Redistribution and use in source and binary forms, with or without modification,
11 are permitted provided that the following conditions are met:
12
13 * Redistributions of source code must retain the above copyright notice, this list
14 of conditions and the following disclaimer.
15
16 * Redistributions in binary form must reproduce the above copyright notice, this
17 list of conditions and the following disclaimer in the documentation and/or other
18 materials provided with the distribution.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
34*/
35
36
37#include "u8x8.h"
38
39
40
41static const uint8_t u8x8_d_ssd1329_128x96_noname_init_seq[] = {
42
43 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
44
45
46 U8X8_C(0x0ae), /* display off */
47 U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
48 U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x03f * 1/64 duty - changed by CREESOO, acc. to datasheet, 100317*/
49 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
50 U8X8_CA(0x0a1, 0x000), /* display start line */
51 U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
52 U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
53 U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
54#ifdef removed
55 U8X8_C(0x0b8), /* set gray scale table */
56 U8X8_A(1), /* */
57 U8X8_A(5), /* */
58 U8X8_A(10), /* */
59 U8X8_A(14), /* */
60 U8X8_A(19), /* */
61 U8X8_A(23), /* */
62 U8X8_A(28), /* */
63 U8X8_A(32), /* */
64 U8X8_A(37), /* */
65 U8X8_A(41), /* */
66 U8X8_A(46), /* */
67 U8X8_A(50), /* */
68 U8X8_A(55), /* */
69 U8X8_A(59), /* */
70 U8X8_A(63), /* */
71#endif
72
73 U8X8_C(0x0b7), /* set default gray scale table */
74
75 U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
76 U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */
77 U8X8_CA(0x0b1, 0x055), /* phase length */
78 U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
79 U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
80 U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
81 U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
82 U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
83 U8X8_C(0x0a4), /* normal display mode */
84
85 U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
86
87 U8X8_END_TRANSFER(), /* disable chip */
88 U8X8_END() /* end of sequence */
89};
90
91static const uint8_t u8x8_d_ssd1329_128x96_nhd_powersave0_seq[] = {
92 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
93 U8X8_C(0x0af), /* display on */
94 U8X8_END_TRANSFER(), /* disable chip */
95 U8X8_END() /* end of sequence */
96};
97
98static const uint8_t u8x8_d_ssd1329_128x96_nhd_powersave1_seq[] = {
99 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
100 U8X8_C(0x0ae), /* display off */
101 U8X8_END_TRANSFER(), /* disable chip */
102 U8X8_END() /* end of sequence */
103};
104
105static const uint8_t u8x8_d_ssd1329_128x96_nhd_flip0_seq[] = {
106 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
107 U8X8_CA(0x0a0, 0x052), /* remap */
108 U8X8_END_TRANSFER(), /* disable chip */
109 U8X8_END() /* end of sequence */
110};
111
112static const uint8_t u8x8_d_ssd1329_128x96_nhd_flip1_seq[] = {
113 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
114 U8X8_CA(0x0a0, 0x041), /* remap */
115 U8X8_END_TRANSFER(), /* disable chip */
116 U8X8_END() /* end of sequence */
117};
118
119
120/*
121 input:
122 one tile (8 Bytes)
123 output:
124 Tile for ssd1329 (32 Bytes)
125*/
126
127static uint8_t u8x8_ssd1329_8to32_dest_buf[32];
128
129static uint8_t *u8x8_ssd1329_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)
130{
131 uint8_t v;
132 uint8_t a,b;
133 uint8_t i, j;
134 uint8_t *dest;
135
136 for( j = 0; j < 4; j++ )
137 {
138 dest = u8x8_ssd1329_8to32_dest_buf;
139 dest += j;
140 a =*ptr;
141 ptr++;
142 b = *ptr;
143 ptr++;
144 for( i = 0; i < 8; i++ )
145 {
146 v = 0;
147 if ( a&1 ) v |= 0xf0;
148 if ( b&1 ) v |= 0x0f;
149 *dest = v;
150 dest+=4;
151 a >>= 1;
152 b >>= 1;
153 }
154 }
155
156 return u8x8_ssd1329_8to32_dest_buf;
157}
158
159
160
161
162static uint8_t u8x8_d_ssd1329_128x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
163{
164 uint8_t x, y, c;
165 uint8_t *ptr;
166 switch(msg)
167 {
168 /* handled by the calling function
169 case U8X8_MSG_DISPLAY_SETUP_MEMORY:
170 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_nhd_display_info);
171 break;
172 */
173 case U8X8_MSG_DISPLAY_INIT:
174 u8x8_d_helper_display_init(u8x8);
175 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_noname_init_seq);
176 break;
177 case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
178 if ( arg_int == 0 )
179 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave0_seq);
180 else
181 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave1_seq);
182 break;
183 case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
184 if ( arg_int == 0 )
185 {
186 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_flip0_seq);
187 u8x8->x_offset = u8x8->display_info->default_x_offset;
188 }
189 else
190 {
191 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_flip1_seq);
192 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
193 }
194 break;
195#ifdef U8X8_WITH_SET_CONTRAST
196 case U8X8_MSG_DISPLAY_SET_CONTRAST:
197 u8x8_cad_StartTransfer(u8x8);
198 u8x8_cad_SendCmd(u8x8, 0x081 );
199 u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1329 has range from 0 to 255 */
200 u8x8_cad_EndTransfer(u8x8);
201 break;
202#endif
203 case U8X8_MSG_DISPLAY_DRAW_TILE:
204 u8x8_cad_StartTransfer(u8x8);
205 x = ((u8x8_tile_t *)arg_ptr)->x_pos;
206 x *= 4;
207
208 y = (((u8x8_tile_t *)arg_ptr)->y_pos);
209
210 y *= 8;
211 y += u8x8->x_offset; /* x_offset is used as y offset for the ssd1329 */
212
213
214 do
215 {
216 c = ((u8x8_tile_t *)arg_ptr)->cnt;
217 ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;
218
219 do
220 {
221 if ( ptr[0] | ptr[1] | ptr[2] | ptr[3] | ptr[4] | ptr[5] | ptr[6] | ptr[7] )
222 {
223 /* draw the tile if pattern is not zero for all bytes */
224 u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */
225 u8x8_cad_SendArg(u8x8, x ); /* start */
226 u8x8_cad_SendArg(u8x8, x+3 ); /* end */
227
228 u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address */
229 u8x8_cad_SendArg(u8x8, y);
230 u8x8_cad_SendArg(u8x8, y+7);
231
232
233 u8x8_cad_SendData(u8x8, 32, u8x8_ssd1329_8to32(u8x8, ptr));
234 }
235 else
236 {
237 /* tile is empty, use the graphics acceleration command */
238 /* are this really available on the SSD1329??? */
239 u8x8_cad_SendCmd(u8x8, 0x024 ); // draw rectangle
240 u8x8_cad_SendArg(u8x8, x );
241 u8x8_cad_SendArg(u8x8, y );
242 u8x8_cad_SendArg(u8x8, x+3 );
243 u8x8_cad_SendArg(u8x8, y+7 );
244 u8x8_cad_SendArg(u8x8, 0 ); // clear
245 }
246 ptr += 8;
247 x += 4;
248 c--;
249 } while( c > 0 );
250
251 //x += 4;
252 arg_int--;
253 } while( arg_int > 0 );
254
255 u8x8_cad_EndTransfer(u8x8);
256 break;
257 default:
258 return 0;
259 }
260 return 1;
261}
262
263
264static const u8x8_display_info_t u8x8_ssd1329_128x96_display_info =
265{
266 /* chip_enable_level = */ 0,
267 /* chip_disable_level = */ 1,
268
269 /* post_chip_enable_wait_ns = */ 20,
270 /* pre_chip_disable_wait_ns = */ 15,
271 /* reset_pulse_width_ms = */ 100,
272 /* post_reset_wait_ms = */ 100, /**/
273 /* sda_setup_time_ns = */ 100, /* ssd1329 */
274 /* sck_pulse_width_ns = */ 100, /* ssd1329 */
275 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
276 /* spi_mode = */ 0, /* active high, rising edge */
277 /* i2c_bus_clock_100kHz = */ 4,
278 /* data_setup_time_ns = */ 40,
279 /* write_pulse_width_ns = */ 60, /* ssd1329 */
280 /* tile_width = */ 16,
281 /* tile_height = */ 12,
282 /* default_x_offset = */ 0, /* x_offset is used as y offset for the ssd1329 */
283 /* flipmode_x_offset = */ 0, /* x_offset is used as y offset for the ssd1329 */
284 /* pixel_width = */ 128,
285 /* pixel_height = */ 96
286};
287
288uint8_t u8x8_d_ssd1329_128x96_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
289{
290 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
291 {
292 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_display_info);
293 return 1;
294 }
295 return u8x8_d_ssd1329_128x96_generic(u8x8, msg, arg_int, arg_ptr);
296}
297
298/*=================================================*/
299/*
300 SSD1329 with 96x96
301 For this display, the x_offset has been reverted to its original meaning!
302
303 https://github.com/olikraus/u8g2/issues/1511
304
305 FlipMode 1 probably does not work, see issue
306*/
307
308static const uint8_t u8x8_d_ssd1329_96x96_flip0_seq[] = {
309 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
310 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
311 U8X8_CA(0x0a1, 0x000), /* display start line */
312 U8X8_CA(0x0a0, 0x042), /* remap */
313 U8X8_END_TRANSFER(), /* disable chip */
314 U8X8_END() /* end of sequence */
315};
316
317static const uint8_t u8x8_d_ssd1329_96x96_flip1_seq[] = {
318 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
319 U8X8_CA(0x0a2, 0x060), /* display offset, shift mapping ram counter */
320 U8X8_CA(0x0a1, 0x000), /* display start line */
321 U8X8_CA(0x0a0, 0x051), /* remap */
322 U8X8_END_TRANSFER(), /* disable chip */
323 U8X8_END() /* end of sequence */
324};
325
326
327static const uint8_t u8x8_d_ssd1329_96x96_noname_init_seq[] = {
328
329 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
330
331
332 U8X8_C(0x0ae), /* display off */
333 U8X8_CA(0x0b3, 0x0f0), /* set display clock divide ratio/oscillator frequency, see #1511*/
334 U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x03f * 1/64 duty */
335 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
336 U8X8_CA(0x0a1, 0x000), /* display start line */
337 U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
338 U8X8_CA(0x0a0, 0x042), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
339 U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
340#ifdef removed
341 U8X8_C(0x0b8), /* set gray scale table */
342 U8X8_A(1), /* */
343 U8X8_A(5), /* */
344 U8X8_A(10), /* */
345 U8X8_A(14), /* */
346 U8X8_A(19), /* */
347 U8X8_A(23), /* */
348 U8X8_A(28), /* */
349 U8X8_A(32), /* */
350 U8X8_A(37), /* */
351 U8X8_A(41), /* */
352 U8X8_A(46), /* */
353 U8X8_A(50), /* */
354 U8X8_A(55), /* */
355 U8X8_A(59), /* */
356 U8X8_A(63), /* */
357#endif
358
359 U8X8_C(0x0b7), /* set default gray scale table */
360
361 U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..255 */
362 U8X8_CA(0x0b2, 0x023), /* frame frequency (row period), see #1511 */
363 U8X8_CA(0x0b1, 0x021), /* phase length, see #1511 */
364 U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
365 U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
366 U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
367 U8X8_CA(0x0be, 0x01f), /* VCOMH voltage */
368 U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
369 U8X8_C(0x0a4), /* normal display mode */
370
371 U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
372
373 U8X8_END_TRANSFER(), /* disable chip */
374 U8X8_END() /* end of sequence */
375};
376
377
378
379static uint8_t u8x8_d_ssd1329_96x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
380{
381 uint8_t x, y, c;
382 uint8_t *ptr;
383 switch(msg)
384 {
385 /* handled by the calling function
386 case U8X8_MSG_DISPLAY_SETUP_MEMORY:
387 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_nhd_display_info);
388 break;
389 */
390 case U8X8_MSG_DISPLAY_INIT:
391 u8x8_d_helper_display_init(u8x8);
392 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_96x96_noname_init_seq);
393 break;
394 case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
395 if ( arg_int == 0 )
396 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave0_seq);
397 else
398 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave1_seq);
399 break;
400 case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
401 if ( arg_int == 0 )
402 {
403 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_96x96_flip0_seq);
404 u8x8->x_offset = u8x8->display_info->default_x_offset;
405 }
406 else
407 {
408 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_96x96_flip1_seq);
409 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
410 }
411 break;
412#ifdef U8X8_WITH_SET_CONTRAST
413 case U8X8_MSG_DISPLAY_SET_CONTRAST:
414 u8x8_cad_StartTransfer(u8x8);
415 u8x8_cad_SendCmd(u8x8, 0x081 );
416 u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1329 has range from 0 to 255 */
417 u8x8_cad_EndTransfer(u8x8);
418 break;
419#endif
420 case U8X8_MSG_DISPLAY_DRAW_TILE:
421 u8x8_cad_StartTransfer(u8x8);
422 x = ((u8x8_tile_t *)arg_ptr)->x_pos;
423 x *= 4;
424 x += u8x8->x_offset;
425
426 y = (((u8x8_tile_t *)arg_ptr)->y_pos);
427
428 y *= 8;
429
430
431 do
432 {
433 c = ((u8x8_tile_t *)arg_ptr)->cnt;
434 ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;
435
436 do
437 {
438 if ( ptr[0] | ptr[1] | ptr[2] | ptr[3] | ptr[4] | ptr[5] | ptr[6] | ptr[7] )
439 {
440 /* draw the tile if pattern is not zero for all bytes */
441 u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */
442 u8x8_cad_SendArg(u8x8, x ); /* start */
443 u8x8_cad_SendArg(u8x8, x+3 ); /* end */
444
445 u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address */
446 u8x8_cad_SendArg(u8x8, y);
447 u8x8_cad_SendArg(u8x8, y+7);
448
449
450 u8x8_cad_SendData(u8x8, 32, u8x8_ssd1329_8to32(u8x8, ptr));
451 }
452 else
453 {
454 /* tile is empty, use the graphics acceleration command */
455 /* are this really available on the SSD1329??? */
456 u8x8_cad_SendCmd(u8x8, 0x024 ); // draw rectangle
457 u8x8_cad_SendArg(u8x8, x );
458 u8x8_cad_SendArg(u8x8, y );
459 u8x8_cad_SendArg(u8x8, x+3 );
460 u8x8_cad_SendArg(u8x8, y+7 );
461 u8x8_cad_SendArg(u8x8, 0 ); // clear
462 }
463 ptr += 8;
464 x += 4;
465 c--;
466 } while( c > 0 );
467
468 //x += 4;
469 arg_int--;
470 } while( arg_int > 0 );
471
472 u8x8_cad_EndTransfer(u8x8);
473 break;
474 default:
475 return 0;
476 }
477 return 1;
478}
479
480
481static const u8x8_display_info_t u8x8_ssd1329_96x96_display_info =
482{
483 /* chip_enable_level = */ 0,
484 /* chip_disable_level = */ 1,
485
486 /* post_chip_enable_wait_ns = */ 20,
487 /* pre_chip_disable_wait_ns = */ 15,
488 /* reset_pulse_width_ms = */ 100,
489 /* post_reset_wait_ms = */ 100, /**/
490 /* sda_setup_time_ns = */ 100, /* ssd1329 */
491 /* sck_pulse_width_ns = */ 100, /* ssd1329 */
492 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
493 /* spi_mode = */ 0, /* active high, rising edge */
494 /* i2c_bus_clock_100kHz = */ 4,
495 /* data_setup_time_ns = */ 40,
496 /* write_pulse_width_ns = */ 60, /* ssd1329 */
497 /* tile_width = */ 12,
498 /* tile_height = */ 12,
499 /* default_x_offset = */ 0, /* x offset for flip mode 0 */
500 /* flipmode_x_offset = */ 16, /* x offset for flip mode 1 */
501 /* pixel_width = */ 96,
502 /* pixel_height = */ 96
503};
504
505uint8_t u8x8_d_ssd1329_96x96_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
506{
507 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
508 {
509 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_96x96_display_info);
510 return 1;
511 }
512 return u8x8_d_ssd1329_96x96_generic(u8x8, msg, arg_int, arg_ptr);
513}