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orion-rf.piolibdepsesp32-s3-n16r8RF24RF24.cpp

2209 lines · 72.1 KB · C++

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1/*
2 Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
3
4 This program is free software; you can redistribute it and/or
5 modify it under the terms of the GNU General Public License
6 version 2 as published by the Free Software Foundation.
7 */
8
9#include "nRF24L01.h"
10#include "RF24_config.h"
11#include "RF24.h"
12
13/****************************************************************************/
14
15void RF24::csn(bool mode)
16{
17#if defined(RF24_TINY)
18 if (ce_pin != csn_pin) {
19 digitalWrite(csn_pin, mode);
20 }
21 else {
22 if (mode == HIGH) {
23 PORTB |= (1 << PINB2); // SCK->CSN HIGH
24 delayMicroseconds(RF24_CSN_SETTLE_HIGH_DELAY); // allow csn to settle.
25 }
26 else {
27 PORTB &= ~(1 << PINB2); // SCK->CSN LOW
28 delayMicroseconds(RF24_CSN_SETTLE_LOW_DELAY); // allow csn to settle
29 }
30 }
31 // Return, CSN toggle complete
32 return;
33
34#elif defined(ARDUINO) && !defined(RF24_SPI_TRANSACTIONS)
35 // Minimum ideal SPI bus speed is 2x data rate
36 // If we assume 2Mbs data rate and 16Mhz clock, a
37 // divider of 4 is the minimum we want.
38 // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
39
40 #if !defined(SOFTSPI)
41 // applies to SPI_UART and inherent hardware SPI
42 #if defined(RF24_SPI_PTR)
43 _spi->setBitOrder(MSBFIRST);
44 _spi->setDataMode(SPI_MODE0);
45
46 #if !defined(F_CPU) || F_CPU < 20000000
47 _spi->setClockDivider(SPI_CLOCK_DIV2);
48 #elif F_CPU < 40000000
49 _spi->setClockDivider(SPI_CLOCK_DIV4);
50 #elif F_CPU < 80000000
51 _spi->setClockDivider(SPI_CLOCK_DIV8);
52 #elif F_CPU < 160000000
53 _spi->setClockDivider(SPI_CLOCK_DIV16);
54 #elif F_CPU < 320000000
55 _spi->setClockDivider(SPI_CLOCK_DIV32);
56 #elif F_CPU < 640000000
57 _spi->setClockDivider(SPI_CLOCK_DIV64);
58 #elif F_CPU < 1280000000
59 _spi->setClockDivider(SPI_CLOCK_DIV128);
60 #else // F_CPU >= 1280000000
61 #error "Unsupported CPU frequency. Please set correct SPI divider."
62 #endif // F_CPU to SPI_CLOCK_DIV translation
63
64 #else // !defined(RF24_SPI_PTR)
65 _SPI.setBitOrder(MSBFIRST);
66 _SPI.setDataMode(SPI_MODE0);
67
68 #if !defined(F_CPU) || F_CPU < 20000000
69 _SPI.setClockDivider(SPI_CLOCK_DIV2);
70 #elif F_CPU < 40000000
71 _SPI.setClockDivider(SPI_CLOCK_DIV4);
72 #elif F_CPU < 80000000
73 _SPI.setClockDivider(SPI_CLOCK_DIV8);
74 #elif F_CPU < 160000000
75 _SPI.setClockDivider(SPI_CLOCK_DIV16);
76 #elif F_CPU < 320000000
77 _SPI.setClockDivider(SPI_CLOCK_DIV32);
78 #elif F_CPU < 640000000
79 _SPI.setClockDivider(SPI_CLOCK_DIV64);
80 #elif F_CPU < 1280000000
81 _SPI.setClockDivider(SPI_CLOCK_DIV128);
82 #else // F_CPU >= 1280000000
83 #error "Unsupported CPU frequency. Please set correct SPI divider."
84 #endif // F_CPU to SPI_CLOCK_DIV translation
85 #endif // !defined(RF24_SPI_PTR)
86 #endif // !defined(SOFTSPI)
87
88#elif defined(RF24_RPi)
89 if (!mode)
90 _SPI.chipSelect(csn_pin);
91#endif // defined(RF24_RPi)
92
93#if !defined(RF24_LINUX)
94 digitalWrite(csn_pin, mode);
95 delayMicroseconds(csDelay);
96#else
97 static_cast<void>(mode); // ignore -Wunused-parameter
98#endif // !defined(RF24_LINUX)
99}
100
101/****************************************************************************/
102
103void RF24::ce(bool level)
104{
105#ifndef RF24_LINUX
106 //Allow for 3-pin use on ATTiny
107 if (ce_pin != csn_pin) {
108#endif
109 digitalWrite(ce_pin, level);
110#ifndef RF24_LINUX
111 }
112#endif
113}
114
115/****************************************************************************/
116
117inline void RF24::beginTransaction()
118{
119#if defined(RF24_SPI_TRANSACTIONS)
120 #if defined(RF24_SPI_PTR)
121 #if defined(RF24_RP2)
122 _spi->beginTransaction(spi_speed);
123 #else // ! defined (RF24_RP2)
124 _spi->beginTransaction(SPISettings(spi_speed, MSBFIRST, SPI_MODE0));
125 #endif // ! defined (RF24_RP2)
126 #else // !defined(RF24_SPI_PTR)
127 _SPI.beginTransaction(SPISettings(spi_speed, MSBFIRST, SPI_MODE0));
128 #endif // !defined(RF24_SPI_PTR)
129#endif // defined (RF24_SPI_TRANSACTIONS)
130 csn(LOW);
131}
132
133/****************************************************************************/
134
135inline void RF24::endTransaction()
136{
137 csn(HIGH);
138#if defined(RF24_SPI_TRANSACTIONS)
139 #if defined(RF24_SPI_PTR)
140 _spi->endTransaction();
141 #else // !defined(RF24_SPI_PTR)
142 _SPI.endTransaction();
143 #endif // !defined(RF24_SPI_PTR)
144#endif // defined (RF24_SPI_TRANSACTIONS)
145}
146
147/****************************************************************************/
148
149void RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
150{
151#if defined(RF24_LINUX) || defined(RF24_RP2)
152 beginTransaction(); //configures the spi settings for RPi, locks mutex and setting csn low
153 uint8_t* prx = spi_rxbuff;
154 uint8_t* ptx = spi_txbuff;
155 uint8_t size = static_cast<uint8_t>(len + 1); // Add register value to transmit buffer
156
157 *ptx++ = reg;
158
159 while (len--) {
160 *ptx++ = nRF24L01::NOP; // Dummy operation, just for reading
161 }
162
163 #if defined(RF24_RP2)
164 _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
165 #else // !defined (RF24_RP2)
166 _SPI.transfernb(reinterpret_cast<char*>(spi_txbuff), reinterpret_cast<char*>(spi_rxbuff), size);
167 #endif // !defined (RF24_RP2)
168
169 status = *prx++; // status is 1st byte of receive buffer
170
171 // decrement before to skip status byte
172 while (--size) {
173 *buf++ = *prx++;
174 }
175
176 endTransaction(); // unlocks mutex and setting csn high
177
178#else // !defined(RF24_LINUX) && !defined(RF24_RP2)
179
180 beginTransaction();
181 #if defined(RF24_SPI_PTR)
182 status = _spi->transfer(reg);
183 while (len--) {
184 *buf++ = _spi->transfer(0xFF);
185 }
186
187 #else // !defined(RF24_SPI_PTR)
188 status = _SPI.transfer(reg);
189 while (len--) {
190 *buf++ = _SPI.transfer(0xFF);
191 }
192
193 #endif // !defined(RF24_SPI_PTR)
194 endTransaction();
195#endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
196}
197
198/****************************************************************************/
199
200uint8_t RF24::read_register(uint8_t reg)
201{
202 uint8_t result;
203
204#if defined(RF24_LINUX) || defined(RF24_RP2)
205 beginTransaction();
206
207 uint8_t* prx = spi_rxbuff;
208 uint8_t* ptx = spi_txbuff;
209 *ptx++ = reg;
210 *ptx++ = nRF24L01::NOP; // Dummy operation, just for reading
211
212 #if defined(RF24_RP2)
213 _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, 2);
214 #else // !defined(RF24_RP2)
215 _SPI.transfernb(reinterpret_cast<char*>(spi_txbuff), reinterpret_cast<char*>(spi_rxbuff), 2);
216 #endif // !defined(RF24_RP2)
217
218 status = *prx; // status is 1st byte of receive buffer
219 result = *++prx; // result is 2nd byte of receive buffer
220
221 endTransaction();
222#else // !defined(RF24_LINUX) && !defined(RF24_RP2)
223
224 beginTransaction();
225 #if defined(RF24_SPI_PTR)
226 status = _spi->transfer(reg);
227 result = _spi->transfer(0xff);
228
229 #else // !defined(RF24_SPI_PTR)
230 status = _SPI.transfer(reg);
231 result = _SPI.transfer(0xff);
232
233 #endif // !defined(RF24_SPI_PTR)
234 endTransaction();
235#endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
236
237 return result;
238}
239
240/****************************************************************************/
241
242void RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
243{
244#if defined(RF24_LINUX) || defined(RF24_RP2)
245 beginTransaction();
246 uint8_t* prx = spi_rxbuff;
247 uint8_t* ptx = spi_txbuff;
248 uint8_t size = static_cast<uint8_t>(len + 1); // Add register value to transmit buffer
249
250 *ptx++ = (nRF24L01::W_REGISTER | reg);
251 while (len--) {
252 *ptx++ = *buf++;
253 }
254
255 #if defined(RF24_RP2)
256 _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
257 #else // !defined(RF24_RP2)
258 _SPI.transfernb(reinterpret_cast<char*>(spi_txbuff), reinterpret_cast<char*>(spi_rxbuff), size);
259 #endif // !defined(RF24_RP2)
260
261 status = *prx; // status is 1st byte of receive buffer
262 endTransaction();
263#else // !defined(RF24_LINUX) && !defined(RF24_RP2)
264
265 beginTransaction();
266 #if defined(RF24_SPI_PTR)
267 status = _spi->transfer(nRF24L01::W_REGISTER | reg);
268 while (len--) {
269 _spi->transfer(*buf++);
270 }
271
272 #else // !defined(RF24_SPI_PTR)
273 status = _SPI.transfer(nRF24L01::W_REGISTER | reg);
274 while (len--) {
275 _SPI.transfer(*buf++);
276 }
277
278 #endif // !defined(RF24_SPI_PTR)
279 endTransaction();
280#endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
281}
282
283/****************************************************************************/
284
285void RF24::write_register(uint8_t reg, uint8_t value)
286{
287 IF_RF24_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"), reg, value));
288#if defined(RF24_LINUX) || defined(RF24_RP2)
289 beginTransaction();
290 uint8_t* prx = spi_rxbuff;
291 uint8_t* ptx = spi_txbuff;
292 *ptx++ = (nRF24L01::W_REGISTER | reg);
293 *ptx = value;
294
295 #if defined(RF24_RP2)
296 _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, 2);
297 #else // !defined(RF24_RP2)
298 _SPI.transfernb(reinterpret_cast<char*>(spi_txbuff), reinterpret_cast<char*>(spi_rxbuff), 2);
299 #endif // !defined(RF24_RP2)
300
301 status = *prx++; // status is 1st byte of receive buffer
302 endTransaction();
303#else // !defined(RF24_LINUX) && !defined(RF24_RP2)
304
305 beginTransaction();
306 #if defined(RF24_SPI_PTR)
307 status = _spi->transfer(nRF24L01::W_REGISTER | reg);
308 _spi->transfer(value);
309 #else // !defined(RF24_SPI_PTR)
310 status = _SPI.transfer(nRF24L01::W_REGISTER | reg);
311 _SPI.transfer(value);
312 #endif // !defined(RF24_SPI_PTR)
313 endTransaction();
314#endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
315}
316
317/****************************************************************************/
318
319void RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
320{
321 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
322
323 uint8_t blank_len = !data_len ? 1 : 0;
324 if (!dynamic_payloads_enabled) {
325 data_len = rf24_min(data_len, payload_size);
326 blank_len = static_cast<uint8_t>(payload_size - data_len);
327 }
328 else {
329 data_len = rf24_min(data_len, static_cast<uint8_t>(32));
330 }
331
332 //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
333 IF_RF24_DEBUG(printf_P("[Writing %u bytes %u blanks]\n", data_len, blank_len););
334
335#if defined(RF24_LINUX) || defined(RF24_RP2)
336 beginTransaction();
337 uint8_t* prx = spi_rxbuff;
338 uint8_t* ptx = spi_txbuff;
339 uint8_t size;
340 size = static_cast<uint8_t>(data_len + blank_len + 1); // Add register value to transmit buffer
341
342 *ptx++ = writeType;
343 while (data_len--) {
344 *ptx++ = *current++;
345 }
346
347 while (blank_len--) {
348 *ptx++ = 0;
349 }
350
351 #if defined(RF24_RP2)
352 _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
353 #else // !defined(RF24_RP2)
354 _SPI.transfernb(reinterpret_cast<char*>(spi_txbuff), reinterpret_cast<char*>(spi_rxbuff), size);
355 #endif // !defined(RF24_RP2)
356
357 status = *prx; // status is 1st byte of receive buffer
358 endTransaction();
359
360#else // !defined(RF24_LINUX) && !defined(RF24_RP2)
361
362 beginTransaction();
363 #if defined(RF24_SPI_PTR)
364 status = _spi->transfer(writeType);
365 while (data_len--) {
366 _spi->transfer(*current++);
367 }
368
369 while (blank_len--) {
370 _spi->transfer(0);
371 }
372
373 #else // !defined(RF24_SPI_PTR)
374 status = _SPI.transfer(writeType);
375 while (data_len--) {
376 _SPI.transfer(*current++);
377 }
378
379 while (blank_len--) {
380 _SPI.transfer(0);
381 }
382
383 #endif // !defined(RF24_SPI_PTR)
384 endTransaction();
385#endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
386}
387
388/****************************************************************************/
389
390void RF24::read_payload(void* buf, uint8_t data_len)
391{
392 uint8_t* current = reinterpret_cast<uint8_t*>(buf);
393
394 uint8_t blank_len = 0;
395 if (!dynamic_payloads_enabled) {
396 data_len = rf24_min(data_len, payload_size);
397 blank_len = static_cast<uint8_t>(payload_size - data_len);
398 }
399 else {
400 data_len = rf24_min(data_len, static_cast<uint8_t>(32));
401 }
402
403 //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
404
405 IF_RF24_DEBUG(printf_P("[Reading %u bytes %u blanks]\n", data_len, blank_len););
406
407#if defined(RF24_LINUX) || defined(RF24_RP2)
408 beginTransaction();
409 uint8_t* prx = spi_rxbuff;
410 uint8_t* ptx = spi_txbuff;
411 uint8_t size;
412 size = static_cast<uint8_t>(data_len + blank_len + 1); // Add register value to transmit buffer
413
414 *ptx++ = nRF24L01::R_RX_PAYLOAD;
415 while (--size) {
416 *ptx++ = nRF24L01::NOP;
417 }
418
419 size = static_cast<uint8_t>(data_len + blank_len + 1); // Size has been lost during while, re affect
420
421 #if defined(RF24_RP2)
422 _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
423 #else // !defined(RF24_RP2)
424 _SPI.transfernb(reinterpret_cast<char*>(spi_txbuff), reinterpret_cast<char*>(spi_rxbuff), size);
425 #endif // !defined(RF24_RP2)
426
427 status = *prx++; // 1st byte is status
428
429 if (data_len > 0) {
430 // Decrement before to skip 1st status byte
431 while (--data_len) {
432 *current++ = *prx++;
433 }
434
435 *current = *prx;
436 }
437 endTransaction();
438#else // !defined(RF24_LINUX) && !defined(RF24_RP2)
439
440 beginTransaction();
441 #if defined(RF24_SPI_PTR)
442 status = _spi->transfer(nRF24L01::R_RX_PAYLOAD);
443 while (data_len--) {
444 *current++ = _spi->transfer(0xFF);
445 }
446
447 while (blank_len--) {
448 _spi->transfer(0xFF);
449 }
450
451 #else // !defined(RF24_SPI_PTR)
452 status = _SPI.transfer(nRF24L01::R_RX_PAYLOAD);
453 while (data_len--) {
454 *current++ = _SPI.transfer(0xFF);
455 }
456
457 while (blank_len--) {
458 _SPI.transfer(0xff);
459 }
460
461 #endif // !defined(RF24_SPI_PTR)
462 endTransaction();
463
464#endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
465}
466
467/****************************************************************************/
468
469uint8_t RF24::flush_rx(void)
470{
471 read_register(nRF24L01::FLUSH_RX, (uint8_t*)nullptr, 0);
472 IF_RF24_DEBUG(printf_P("[Flushing RX FIFO]"););
473 return status;
474}
475
476/****************************************************************************/
477
478uint8_t RF24::flush_tx(void)
479{
480 read_register(nRF24L01::FLUSH_TX, (uint8_t*)nullptr, 0);
481 IF_RF24_DEBUG(printf_P("[Flushing RX FIFO]"););
482 return status;
483}
484
485/****************************************************************************/
486#if !defined(MINIMAL)
487
488void RF24::printStatus(uint8_t flags)
489{
490 printf_P(PSTR("RX_DR=%x TX_DS=%x TX_DF=%x RX_PIPE=%x TX_FULL=%x\r\n"),
491 (flags & RF24_RX_DR) ? 1 : 0,
492 (flags & RF24_TX_DS) ? 1 : 0,
493 (flags & RF24_TX_DF) ? 1 : 0,
494 (flags >> nRF24L01::RX_P_NO) & 0x07,
495 (flags & _BV(nRF24L01::TX_FULL)) ? 1 : 0);
496}
497
498/****************************************************************************/
499
500void RF24::print_observe_tx(uint8_t value)
501{
502 printf_P(PSTR("OBSERVE_TX=%02x: PLOS_CNT=%x ARC_CNT=%x\r\n"), value, (value >> nRF24L01::PLOS_CNT) & 0x0F, (value >> nRF24L01::ARC_CNT) & 0x0F);
503}
504
505/****************************************************************************/
506
507void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
508{
509 printf_P(PSTR(PRIPSTR
510 "\t="),
511 name);
512 while (qty--) {
513 printf_P(PSTR(" 0x%02x"), read_register(reg++));
514 }
515 printf_P(PSTR("\r\n"));
516}
517
518/****************************************************************************/
519
520void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
521{
522
523 printf_P(PSTR(PRIPSTR
524 "\t="),
525 name);
526 while (qty--) {
527 uint8_t* buffer = new uint8_t[addr_width];
528 read_register(reg++, buffer, addr_width);
529
530 printf_P(PSTR(" 0x"));
531 uint8_t* bufptr = buffer + addr_width;
532 while (--bufptr >= buffer) {
533 printf_P(PSTR("%02x"), *bufptr); // NOLINT: clang-tidy seems to emit a false positive about zero-allocated memory here (*bufptr)
534 }
535 delete[] buffer;
536 }
537 printf_P(PSTR("\r\n"));
538}
539
540/****************************************************************************/
541
542uint8_t RF24::sprintf_address_register(char* out_buffer, uint8_t reg, uint8_t qty)
543{
544 uint8_t offset = 0;
545 uint8_t* read_buffer = new uint8_t[addr_width];
546 while (qty--) {
547 read_register(reg++, read_buffer, addr_width);
548 uint8_t* bufptr = read_buffer + addr_width;
549 while (--bufptr >= read_buffer) {
550 offset += sprintf_P(out_buffer + offset, PSTR("%02X"), *bufptr); // NOLINT(clang-analyzer-cplusplus.NewDelete)
551 }
552 }
553 delete[] read_buffer;
554 return offset;
555}
556#endif // !defined(MINIMAL)
557
558/****************************************************************************/
559
560RF24::RF24(rf24_gpio_pin_t _cepin, rf24_gpio_pin_t _cspin, uint32_t _spi_speed)
561 : ce_pin(_cepin),
562 csn_pin(_cspin),
563 spi_speed(_spi_speed),
564 payload_size(32),
565 _is_p_variant(false),
566 _is_p0_rx(false),
567 addr_width(5),
568 dynamic_payloads_enabled(true),
569#if defined FAILURE_HANDLING
570 failureDetected(0),
571#endif
572 csDelay(5)
573{
574 _init_obj();
575}
576
577/****************************************************************************/
578
579RF24::RF24(uint32_t _spi_speed)
580 : ce_pin(RF24_PIN_INVALID),
581 csn_pin(RF24_PIN_INVALID),
582 spi_speed(_spi_speed),
583 payload_size(32),
584 _is_p_variant(false),
585 _is_p0_rx(false),
586 addr_width(5),
587 dynamic_payloads_enabled(true),
588#if defined FAILURE_HANDLING
589 failureDetected(0),
590#endif
591 csDelay(5)
592{
593 _init_obj();
594}
595
596/****************************************************************************/
597
598void RF24::_init_obj()
599{
600 // Use a pointer on the Arduino platform
601
602#if defined(RF24_SPI_PTR) && !defined(RF24_RP2)
603 _spi = &SPI;
604#endif // defined (RF24_SPI_PTR)
605
606 if (spi_speed <= 35000) { //Handle old BCM2835 speed constants, default to RF24_SPI_SPEED
607 spi_speed = RF24_SPI_SPEED;
608 }
609}
610
611/****************************************************************************/
612
613void RF24::setChannel(uint8_t channel)
614{
615 const uint8_t max_channel = 125;
616 write_register(nRF24L01::RF_CH, rf24_min(channel, max_channel));
617}
618
619uint8_t RF24::getChannel()
620{
621 return read_register(nRF24L01::RF_CH);
622}
623
624/****************************************************************************/
625
626void RF24::setPayloadSize(uint8_t size)
627{
628 // payload size must be in range [1, 32]
629 payload_size = static_cast<uint8_t>(rf24_max(1, rf24_min(32, size)));
630
631 // write static payload size setting for all pipes
632 for (uint8_t i = 0; i < 6; ++i) {
633 write_register(static_cast<uint8_t>(nRF24L01::RX_PW_P0 + i), payload_size);
634 }
635}
636
637/****************************************************************************/
638
639uint8_t RF24::getPayloadSize(void)
640{
641 return payload_size;
642}
643
644/****************************************************************************/
645
646#if !defined(MINIMAL)
647
648static const PROGMEM char rf24_datarate_e_str_0[] = "= 1 MBPS";
649static const PROGMEM char rf24_datarate_e_str_1[] = "= 2 MBPS";
650static const PROGMEM char rf24_datarate_e_str_2[] = "= 250 KBPS";
651static const PROGMEM char* const rf24_datarate_e_str_P[] = {
652 rf24_datarate_e_str_0,
653 rf24_datarate_e_str_1,
654 rf24_datarate_e_str_2,
655};
656static const PROGMEM char rf24_model_e_str_0[] = "nRF24L01";
657static const PROGMEM char rf24_model_e_str_1[] = "nRF24L01+";
658static const PROGMEM char* const rf24_model_e_str_P[] = {
659 rf24_model_e_str_0,
660 rf24_model_e_str_1,
661};
662static const PROGMEM char rf24_crclength_e_str_0[] = "= Disabled";
663static const PROGMEM char rf24_crclength_e_str_1[] = "= 8 bits";
664static const PROGMEM char rf24_crclength_e_str_2[] = "= 16 bits";
665static const PROGMEM char* const rf24_crclength_e_str_P[] = {
666 rf24_crclength_e_str_0,
667 rf24_crclength_e_str_1,
668 rf24_crclength_e_str_2,
669};
670static const PROGMEM char rf24_pa_dbm_e_str_0[] = "= PA_MIN";
671static const PROGMEM char rf24_pa_dbm_e_str_1[] = "= PA_LOW";
672static const PROGMEM char rf24_pa_dbm_e_str_2[] = "= PA_HIGH";
673static const PROGMEM char rf24_pa_dbm_e_str_3[] = "= PA_MAX";
674static const PROGMEM char* const rf24_pa_dbm_e_str_P[] = {
675 rf24_pa_dbm_e_str_0,
676 rf24_pa_dbm_e_str_1,
677 rf24_pa_dbm_e_str_2,
678 rf24_pa_dbm_e_str_3,
679};
680
681static const PROGMEM char rf24_feature_e_str_on[] = "= Enabled";
682static const PROGMEM char rf24_feature_e_str_allowed[] = "= Allowed";
683static const PROGMEM char rf24_feature_e_str_open[] = " open ";
684static const PROGMEM char rf24_feature_e_str_closed[] = "closed";
685static const PROGMEM char* const rf24_feature_e_str_P[] = {
686 rf24_crclength_e_str_0,
687 rf24_feature_e_str_on,
688 rf24_feature_e_str_allowed,
689 rf24_feature_e_str_closed,
690 rf24_feature_e_str_open,
691};
692
693void RF24::printDetails(void)
694{
695
696 #if defined(RF24_LINUX)
697 printf("================ SPI Configuration ================\n");
698 uint8_t bus_ce = static_cast<uint8_t>(csn_pin % 10);
699 uint8_t bus_numb = static_cast<uint8_t>((csn_pin - bus_ce) / 10);
700 printf("CSN Pin\t\t= /dev/spidev%d.%d\n", bus_numb, bus_ce);
701 printf("CE Pin\t\t= Custom GPIO%d\n", ce_pin);
702 #endif
703 printf_P(PSTR("SPI Speedz\t= %d Mhz\n"), static_cast<uint8_t>(spi_speed / 1000000)); //Print the SPI speed on non-Linux devices
704 #if defined(RF24_LINUX)
705 printf("================ NRF Configuration ================\n");
706 #endif // defined(RF24_LINUX)
707
708 uint8_t status = update();
709 printf_P(PSTR("STATUS\t\t= 0x%02x "), status);
710 printStatus(status);
711
712 print_address_register(PSTR("RX_ADDR_P0-1"), nRF24L01::RX_ADDR_P0, 2);
713 print_byte_register(PSTR("RX_ADDR_P2-5"), nRF24L01::RX_ADDR_P2, 4);
714 print_address_register(PSTR("TX_ADDR\t"), nRF24L01::TX_ADDR);
715
716 print_byte_register(PSTR("RX_PW_P0-6"), nRF24L01::RX_PW_P0, 6);
717 print_byte_register(PSTR("EN_AA\t"), nRF24L01::EN_AA);
718 print_byte_register(PSTR("EN_RXADDR"), nRF24L01::EN_RXADDR);
719 print_byte_register(PSTR("RF_CH\t"), nRF24L01::RF_CH);
720 print_byte_register(PSTR("RF_SETUP"), nRF24L01::RF_SETUP);
721 print_byte_register(PSTR("CONFIG\t"), nRF24L01::CONFIG);
722 print_byte_register(PSTR("DYNPD/FEATURE"), nRF24L01::DYNPD, 2);
723
724 printf_P(PSTR("Data Rate\t" PRIPSTR
725 "\r\n"),
726 (char*)(pgm_read_ptr(&rf24_datarate_e_str_P[getDataRate()])));
727 printf_P(PSTR("Model\t\t= " PRIPSTR
728 "\r\n"),
729 (char*)(pgm_read_ptr(&rf24_model_e_str_P[isPVariant()])));
730 printf_P(PSTR("CRC Length\t" PRIPSTR
731 "\r\n"),
732 (char*)(pgm_read_ptr(&rf24_crclength_e_str_P[getCRCLength()])));
733 printf_P(PSTR("PA Power\t" PRIPSTR
734 "\r\n"),
735 (char*)(pgm_read_ptr(&rf24_pa_dbm_e_str_P[getPALevel()])));
736 printf_P(PSTR("ARC\t\t= %d\r\n"), getARC());
737}
738
739void RF24::printPrettyDetails(void)
740{
741
742 #if defined(RF24_LINUX)
743 printf("================ SPI Configuration ================\n");
744 uint8_t bus_ce = static_cast<uint8_t>(csn_pin % 10);
745 uint8_t bus_numb = static_cast<uint8_t>((csn_pin - bus_ce) / 10);
746 printf("CSN Pin\t\t\t= /dev/spidev%d.%d\n", bus_numb, bus_ce);
747 printf("CE Pin\t\t\t= Custom GPIO%d\n", ce_pin);
748 #endif
749 printf_P(PSTR("SPI Frequency\t\t= %d Mhz\n"), static_cast<uint8_t>(spi_speed / 1000000)); //Print the SPI speed on non-Linux devices
750 #if defined(RF24_LINUX)
751 printf("================ NRF Configuration ================\n");
752 #endif // defined(RF24_LINUX)
753
754 uint8_t channel = getChannel();
755 uint16_t frequency = static_cast<uint16_t>(channel + 2400);
756 printf_P(PSTR("Channel\t\t\t= %u (~ %u MHz)\r\n"), channel, frequency);
757 printf_P(PSTR("Model\t\t\t= " PRIPSTR
758 "\r\n"),
759 (char*)(pgm_read_ptr(&rf24_model_e_str_P[isPVariant()])));
760
761 printf_P(PSTR("RF Data Rate\t\t" PRIPSTR
762 "\r\n"),
763 (char*)(pgm_read_ptr(&rf24_datarate_e_str_P[getDataRate()])));
764 printf_P(PSTR("RF Power Amplifier\t" PRIPSTR
765 "\r\n"),
766 (char*)(pgm_read_ptr(&rf24_pa_dbm_e_str_P[getPALevel()])));
767 printf_P(PSTR("RF Low Noise Amplifier\t" PRIPSTR
768 "\r\n"),
769 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>((read_register(nRF24L01::RF_SETUP) & 1) * 1)])));
770 printf_P(PSTR("CRC Length\t\t" PRIPSTR
771 "\r\n"),
772 (char*)(pgm_read_ptr(&rf24_crclength_e_str_P[getCRCLength()])));
773 printf_P(PSTR("Address Length\t\t= %d bytes\r\n"), (read_register(nRF24L01::SETUP_AW) & 3) + 2);
774 printf_P(PSTR("Static Payload Length\t= %d bytes\r\n"), getPayloadSize());
775
776 uint8_t setupRetry = read_register(nRF24L01::SETUP_RETR);
777 printf_P(PSTR("Auto Retry Delay\t= %d microseconds\r\n"), (setupRetry >> nRF24L01::ARD) * 250 + 250);
778 printf_P(PSTR("Auto Retry Attempts\t= %d maximum\r\n"), setupRetry & 0x0F);
779
780 uint8_t observeTx = read_register(nRF24L01::OBSERVE_TX);
781 printf_P(PSTR("Packets lost on\n current channel\t= %d\r\n"), observeTx >> 4);
782 printf_P(PSTR("Retry attempts made for\n last transmission\t= %d\r\n"), observeTx & 0x0F);
783
784 uint8_t features = read_register(nRF24L01::FEATURE);
785 printf_P(PSTR("Multicast\t\t" PRIPSTR
786 "\r\n"),
787 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>(static_cast<bool>(features & _BV(nRF24L01::EN_DYN_ACK)) * 2)])));
788 printf_P(PSTR("Custom ACK Payload\t" PRIPSTR
789 "\r\n"),
790 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>(static_cast<bool>(features & _BV(nRF24L01::EN_ACK_PAY)) * 1)])));
791
792 uint8_t dynPl = read_register(nRF24L01::DYNPD);
793 printf_P(PSTR("Dynamic Payloads\t" PRIPSTR
794 "\r\n"),
795 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>((dynPl && (features & _BV(nRF24L01::EN_DPL))) * 1)])));
796
797 uint8_t autoAck = read_register(nRF24L01::EN_AA);
798 if (autoAck == 0x3F || autoAck == 0) {
799 // all pipes have the same configuration about auto-ack feature
800 printf_P(PSTR("Auto Acknowledgment\t" PRIPSTR
801 "\r\n"),
802 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>(static_cast<bool>(autoAck) * 1)])));
803 }
804 else {
805 // representation per pipe
806 printf_P(PSTR("Auto Acknowledgment\t= 0b%c%c%c%c%c%c\r\n"),
807 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P5)) + 48),
808 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P4)) + 48),
809 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P3)) + 48),
810 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P2)) + 48),
811 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P1)) + 48),
812 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P0)) + 48));
813 }
814
815 config_reg = read_register(nRF24L01::CONFIG);
816 printf_P(PSTR("Primary Mode\t\t= %cX\r\n"), config_reg & _BV(nRF24L01::PRIM_RX) ? 'R' : 'T');
817 print_address_register(PSTR("TX address\t"), nRF24L01::TX_ADDR);
818
819 uint8_t openPipes = read_register(nRF24L01::EN_RXADDR);
820 for (uint8_t i = 0; i < 6; ++i) {
821 bool isOpen = openPipes & _BV(i);
822 printf_P(PSTR("pipe %u (" PRIPSTR
823 ") bound"),
824 i, (char*)(pgm_read_ptr(&rf24_feature_e_str_P[isOpen + 3])));
825 if (i < 2) {
826 print_address_register(PSTR(""), static_cast<uint8_t>(nRF24L01::RX_ADDR_P0 + i));
827 }
828 else {
829 print_byte_register(PSTR(""), static_cast<uint8_t>(nRF24L01::RX_ADDR_P0 + i));
830 }
831 }
832}
833
834/****************************************************************************/
835
836uint16_t RF24::sprintfPrettyDetails(char* debugging_information)
837{
838 const char* format_string = PSTR(
839 "================ SPI Configuration ================\n"
840 "CSN Pin\t\t\t= %d\n"
841 "CE Pin\t\t\t= %d\n"
842 "SPI Frequency\t\t= %d Mhz\n"
843 "================ NRF Configuration ================\n"
844 "Channel\t\t\t= %u (~ %u MHz)\n"
845 "RF Data Rate\t\t" PRIPSTR "\n"
846 "RF Power Amplifier\t" PRIPSTR "\n"
847 "RF Low Noise Amplifier\t" PRIPSTR "\n"
848 "CRC Length\t\t" PRIPSTR "\n"
849 "Address Length\t\t= %d bytes\n"
850 "Static Payload Length\t= %d bytes\n"
851 "Auto Retry Delay\t= %d microseconds\n"
852 "Auto Retry Attempts\t= %d maximum\n"
853 "Packets lost on\n current channel\t= %d\r\n"
854 "Retry attempts made for\n last transmission\t= %d\r\n"
855 "Multicast\t\t" PRIPSTR "\n"
856 "Custom ACK Payload\t" PRIPSTR "\n"
857 "Dynamic Payloads\t" PRIPSTR "\n"
858 "Auto Acknowledgment\t");
859 const char* format_str2 = PSTR("\nPrimary Mode\t\t= %cX\nTX address\t\t= 0x");
860 const char* format_str3 = PSTR("\nPipe %d (" PRIPSTR ") bound\t= 0x");
861
862 uint16_t offset = sprintf_P(
863 debugging_information, format_string, csn_pin, ce_pin,
864 static_cast<uint8_t>(spi_speed / 1000000), getChannel(),
865 static_cast<uint16_t>(getChannel() + 2400),
866 (char*)(pgm_read_ptr(&rf24_datarate_e_str_P[getDataRate()])),
867 (char*)(pgm_read_ptr(&rf24_pa_dbm_e_str_P[getPALevel()])),
868 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>((read_register(nRF24L01::RF_SETUP) & 1) * 1)])),
869 (char*)(pgm_read_ptr(&rf24_crclength_e_str_P[getCRCLength()])),
870 ((read_register(nRF24L01::SETUP_AW) & 3) + 2), getPayloadSize(),
871 ((read_register(nRF24L01::SETUP_RETR) >> nRF24L01::ARD) * 250 + 250),
872 (read_register(nRF24L01::SETUP_RETR) & 0x0F), (read_register(nRF24L01::OBSERVE_TX) >> 4),
873 (read_register(nRF24L01::OBSERVE_TX) & 0x0F),
874 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>(static_cast<bool>(read_register(nRF24L01::FEATURE) & _BV(nRF24L01::EN_DYN_ACK)) * 2)])),
875 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>(static_cast<bool>(read_register(nRF24L01::FEATURE) & _BV(nRF24L01::EN_ACK_PAY)) * 1)])),
876 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>((read_register(nRF24L01::DYNPD) && (read_register(nRF24L01::FEATURE) & _BV(nRF24L01::EN_DPL))) * 1)])));
877 uint8_t autoAck = read_register(nRF24L01::EN_AA);
878 if (autoAck == 0x3F || autoAck == 0) {
879 // all pipes have the same configuration about auto-ack feature
880 offset += sprintf_P(
881 debugging_information + offset, PSTR("" PRIPSTR ""),
882 (char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<uint8_t>(static_cast<bool>(autoAck) * 1)])));
883 }
884 else {
885 // representation per pipe
886 offset += sprintf_P(
887 debugging_information + offset, PSTR("= 0b%c%c%c%c%c%c"),
888 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P5)) + 48),
889 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P4)) + 48),
890 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P3)) + 48),
891 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P2)) + 48),
892 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P1)) + 48),
893 static_cast<char>(static_cast<bool>(autoAck & _BV(nRF24L01::ENAA_P0)) + 48));
894 }
895 offset += sprintf_P(
896 debugging_information + offset, format_str2,
897 (read_register(nRF24L01::CONFIG) & _BV(nRF24L01::PRIM_RX) ? 'R' : 'T'));
898 offset += sprintf_address_register(debugging_information + offset, nRF24L01::TX_ADDR);
899 uint8_t openPipes = read_register(nRF24L01::EN_RXADDR);
900 for (uint8_t i = 0; i < 6; ++i) {
901 offset += sprintf_P(
902 debugging_information + offset, format_str3,
903 i, ((char*)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<bool>(openPipes & _BV(i)) + 3]))));
904 if (i < 2) {
905 offset += sprintf_address_register(
906 debugging_information + offset, static_cast<uint8_t>(nRF24L01::RX_ADDR_P0 + i));
907 }
908 else {
909 offset += sprintf_P(
910 debugging_information + offset, PSTR("%02X"),
911 read_register(static_cast<uint8_t>(nRF24L01::RX_ADDR_P0 + i)));
912 }
913 }
914 return offset;
915}
916
917/****************************************************************************/
918
919void RF24::encodeRadioDetails(uint8_t* encoded_details)
920{
921 uint8_t end = nRF24L01::FEATURE + 1;
922 for (uint8_t i = nRF24L01::CONFIG; i < end; ++i) {
923 if (i == nRF24L01::RX_ADDR_P0 || i == nRF24L01::RX_ADDR_P1 || i == nRF24L01::TX_ADDR) {
924 // get 40-bit registers
925 read_register(i, encoded_details, 5);
926 encoded_details += 5;
927 }
928 else if (i != 0x18 && i != 0x19 && i != 0x1a && i != 0x1b) { // skip undocumented registers
929 // get single byte registers
930 *encoded_details++ = read_register(i);
931 }
932 }
933 *encoded_details++ = ce_pin >> 4;
934 *encoded_details++ = ce_pin & 0xFF;
935 *encoded_details++ = csn_pin >> 4;
936 *encoded_details++ = csn_pin & 0xFF;
937 *encoded_details = static_cast<uint8_t>((spi_speed / 1000000) | _BV(_is_p_variant * 4));
938}
939#endif // !defined(MINIMAL)
940
941/****************************************************************************/
942#if defined(RF24_SPI_PTR) || defined(DOXYGEN_FORCED)
943// does not apply to RF24_LINUX
944
945bool RF24::begin(_SPI* spiBus)
946{
947 _spi = spiBus;
948 return _init_pins() && _init_radio();
949}
950
951/****************************************************************************/
952
953bool RF24::begin(_SPI* spiBus, rf24_gpio_pin_t _cepin, rf24_gpio_pin_t _cspin)
954{
955 ce_pin = _cepin;
956 csn_pin = _cspin;
957 return begin(spiBus);
958}
959
960#endif // defined (RF24_SPI_PTR) || defined (DOXYGEN_FORCED)
961
962/****************************************************************************/
963
964bool RF24::begin(rf24_gpio_pin_t _cepin, rf24_gpio_pin_t _cspin)
965{
966 ce_pin = _cepin;
967 csn_pin = _cspin;
968 return begin();
969}
970
971/****************************************************************************/
972
973bool RF24::begin(void)
974{
975#if defined(RF24_LINUX)
976 #if defined(RF24_RPi)
977 switch (csn_pin) { // Ensure valid hardware CS pin
978 case 0: break;
979 case 1: break;
980 // Allow BCM2835 enums for RPi
981 case 8: csn_pin = 0; break;
982 case 7: csn_pin = 1; break;
983 case 18: csn_pin = 10; break; // to make it work on SPI1
984 case 17: csn_pin = 11; break;
985 case 16: csn_pin = 12; break;
986 default: csn_pin = 0; break;
987 }
988 #endif // RF24_RPi
989
990 _SPI.begin(csn_pin, spi_speed);
991
992#elif defined(XMEGA_D3)
993 _spi->begin(csn_pin);
994
995#elif defined(RF24_RP2)
996 _spi = new SPI();
997 _spi->begin(PICO_DEFAULT_SPI ? spi1 : spi0);
998
999#else // using an Arduino platform || defined (LITTLEWIRE)
1000
1001 #if defined(RF24_SPI_PTR)
1002 _spi->begin();
1003 #else // !defined(RF24_SPI_PTR)
1004 _SPI.begin();
1005 #endif // !defined(RF24_SPI_PTR)
1006
1007#endif // !defined(XMEGA_D3) && !defined(RF24_LINUX)
1008
1009 return _init_pins() && _init_radio();
1010}
1011
1012/****************************************************************************/
1013
1014bool RF24::_init_pins()
1015{
1016 if (!isValid()) {
1017 // didn't specify the CSN & CE pins to c'tor nor begin()
1018 return false;
1019 }
1020
1021#if defined(RF24_LINUX)
1022
1023 pinMode(ce_pin, OUTPUT);
1024 ce(LOW);
1025 delay(100);
1026
1027#elif defined(LITTLEWIRE)
1028 pinMode(csn_pin, OUTPUT);
1029 csn(HIGH);
1030
1031#elif defined(XMEGA_D3)
1032 if (ce_pin != csn_pin) {
1033 pinMode(ce_pin, OUTPUT);
1034 };
1035 ce(LOW);
1036 csn(HIGH);
1037 delay(200);
1038
1039#else // using an Arduino platform
1040
1041 // Initialize pins
1042 if (ce_pin != csn_pin) {
1043 pinMode(ce_pin, OUTPUT);
1044 pinMode(csn_pin, OUTPUT);
1045 }
1046
1047 ce(LOW);
1048 csn(HIGH);
1049
1050 #if defined(__ARDUINO_X86__)
1051 delay(100);
1052 #endif
1053#endif // !defined(XMEGA_D3) && !defined(LITTLEWIRE) && !defined(RF24_LINUX)
1054
1055 return true; // assuming pins are connected properly
1056}
1057
1058/****************************************************************************/
1059
1060bool RF24::_init_radio()
1061{
1062 // Must allow the radio time to settle else configuration bits will not necessarily stick.
1063 // This is actually only required following power up but some settling time also appears to
1064 // be required after resets too. For full coverage, we'll always assume the worst.
1065 // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
1066 // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
1067 // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
1068 delay(5);
1069
1070 // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
1071 // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
1072 // sizes must never be used. See datasheet for a more complete explanation.
1073 setRetries(5, 15);
1074
1075 // Then set the data rate to the slowest (and most reliable) speed supported by all hardware.
1076 setDataRate(RF24_1MBPS);
1077
1078 // detect if is a plus variant & use old toggle features command accordingly
1079 uint8_t before_toggle = read_register(nRF24L01::FEATURE);
1080 toggle_features();
1081 uint8_t after_toggle = read_register(nRF24L01::FEATURE);
1082 _is_p_variant = before_toggle == after_toggle;
1083 if (after_toggle) {
1084 if (_is_p_variant) {
1085 // module did not experience power-on-reset (#401)
1086 toggle_features();
1087 }
1088 // allow use of multicast parameter and dynamic payloads by default
1089 write_register(nRF24L01::FEATURE, 0);
1090 }
1091 ack_payloads_enabled = false; // ack payloads disabled by default
1092 write_register(nRF24L01::DYNPD, 0); // disable dynamic payloads by default (for all pipes)
1093 dynamic_payloads_enabled = false;
1094 write_register(nRF24L01::EN_AA, 0x3F); // enable auto-ack on all pipes
1095 write_register(nRF24L01::EN_RXADDR, 3); // only open RX pipes 0 & 1
1096 setPayloadSize(32); // set static payload size to 32 (max) bytes by default
1097 setAddressWidth(5); // set default address length to (max) 5 bytes
1098
1099 // Set up default configuration. Callers can always change it later.
1100 // This channel should be universally safe and not bleed over into adjacent
1101 // spectrum.
1102 setChannel(76);
1103
1104 // Reset current status
1105 // Notice reset and flush is the last thing we do
1106 write_register(nRF24L01::STATUS, RF24_IRQ_ALL);
1107
1108 // Flush buffers
1109 flush_rx();
1110 flush_tx();
1111
1112 // Clear CONFIG register:
1113 // Reflect NO IRQ events on IRQ pin
1114 // Enable PTX
1115 // Power Up
1116 // 16-bit CRC (CRC required by auto-ack)
1117 // Do not write CE high so radio will remain in standby I mode
1118 // PTX should use only 22uA of power
1119 write_register(nRF24L01::CONFIG, (_BV(nRF24L01::EN_CRC) | _BV(nRF24L01::CRCO) | _BV(nRF24L01::MASK_RX_DR) | _BV(nRF24L01::MASK_TX_DS) | _BV(nRF24L01::MASK_MAX_RT)));
1120 config_reg = read_register(nRF24L01::CONFIG);
1121
1122 powerUp();
1123
1124 // if config is not set correctly then there was a bad response from module
1125 return config_reg == (_BV(nRF24L01::EN_CRC) | _BV(nRF24L01::CRCO) | _BV(nRF24L01::PWR_UP) | _BV(nRF24L01::MASK_RX_DR) | _BV(nRF24L01::MASK_TX_DS) | _BV(nRF24L01::MASK_MAX_RT)) ? true : false;
1126}
1127
1128/****************************************************************************/
1129
1130bool RF24::isChipConnected()
1131{
1132 return read_register(nRF24L01::SETUP_AW) == (addr_width - static_cast<uint8_t>(2));
1133}
1134
1135/****************************************************************************/
1136
1137bool RF24::isValid()
1138{
1139 return ce_pin != RF24_PIN_INVALID && csn_pin != RF24_PIN_INVALID;
1140}
1141
1142/****************************************************************************/
1143
1144void RF24::startListening(void)
1145{
1146#if !defined(RF24_TINY) && !defined(LITTLEWIRE)
1147 powerUp();
1148#endif
1149 config_reg |= _BV(nRF24L01::PRIM_RX);
1150 write_register(nRF24L01::CONFIG, config_reg);
1151 write_register(nRF24L01::STATUS, RF24_IRQ_ALL);
1152 ce(HIGH);
1153
1154 // Restore the pipe0 address, if exists
1155 if (_is_p0_rx) {
1156 write_register(nRF24L01::RX_ADDR_P0, pipe0_reading_address, addr_width);
1157 }
1158 else {
1159 closeReadingPipe(0);
1160 }
1161}
1162
1163/****************************************************************************/
1164
1165static const PROGMEM uint8_t child_pipe_enable[] = {nRF24L01::ERX_P0, nRF24L01::ERX_P1, nRF24L01::ERX_P2,
1166 nRF24L01::ERX_P3, nRF24L01::ERX_P4, nRF24L01::ERX_P5};
1167
1168void RF24::stopListening(void)
1169{
1170 ce(LOW);
1171
1172 //delayMicroseconds(100);
1173 delayMicroseconds(static_cast<int>(txDelay));
1174 if (ack_payloads_enabled) {
1175 flush_tx();
1176 }
1177
1178 config_reg = static_cast<uint8_t>(config_reg & ~_BV(nRF24L01::PRIM_RX));
1179 write_register(nRF24L01::CONFIG, config_reg);
1180
1181#if defined(RF24_TINY) || defined(LITTLEWIRE)
1182 // for 3 pins solution TX mode is only left with additional powerDown/powerUp cycle
1183 if (ce_pin == csn_pin) {
1184 powerDown();
1185 powerUp();
1186 }
1187#endif
1188 write_register(nRF24L01::RX_ADDR_P0, pipe0_writing_address, addr_width);
1189 write_register(nRF24L01::EN_RXADDR, static_cast<uint8_t>(read_register(nRF24L01::EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0])))); // Enable RX on pipe0
1190}
1191
1192/****************************************************************************/
1193
1194void RF24::stopListening(const uint64_t txAddress)
1195{
1196 memcpy(pipe0_writing_address, &txAddress, addr_width);
1197 stopListening();
1198 write_register(nRF24L01::TX_ADDR, pipe0_writing_address, addr_width);
1199}
1200
1201/****************************************************************************/
1202
1203void RF24::stopListening(const uint8_t* txAddress)
1204{
1205 memcpy(pipe0_writing_address, txAddress, addr_width);
1206 stopListening();
1207 write_register(nRF24L01::TX_ADDR, pipe0_writing_address, addr_width);
1208}
1209
1210/****************************************************************************/
1211
1212void RF24::powerDown(void)
1213{
1214 ce(LOW); // Guarantee CE is low on powerDown
1215 config_reg = static_cast<uint8_t>(config_reg & ~_BV(nRF24L01::PWR_UP));
1216 write_register(nRF24L01::CONFIG, config_reg);
1217}
1218
1219/****************************************************************************/
1220
1221//Power up now. Radio will not power down unless instructed by MCU for config changes etc.
1222void RF24::powerUp(void)
1223{
1224 // if not powered up then power up and wait for the radio to initialize
1225 if (!(config_reg & _BV(nRF24L01::PWR_UP))) {
1226 config_reg |= _BV(nRF24L01::PWR_UP);
1227 write_register(nRF24L01::CONFIG, config_reg);
1228
1229 // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
1230 // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
1231 // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
1232 delayMicroseconds(RF24_POWERUP_DELAY);
1233 }
1234}
1235
1236/******************************************************************/
1237#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1238
1239void RF24::errNotify()
1240{
1241 #if defined(RF24_DEBUG) || defined(RF24_LINUX)
1242 printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
1243 #endif
1244 #if defined(FAILURE_HANDLING)
1245 failureDetected = 1;
1246 #else
1247 delay(5000);
1248 #endif
1249}
1250
1251/******************************************************************/
1252
1253int8_t RF24::errHandler(bool* doRecovery)
1254{
1255
1256 //Wait until complete or failed
1257 uint32_t timer = millis();
1258
1259 while (!(update() & (RF24_TX_DS | RF24_TX_DF))) {
1260 if (millis() - timer > 95) {
1261 #if defined(FAILURE_HANDLING)
1262 flush_rx();
1263 flush_tx();
1264 if (doRecovery) {
1265 *doRecovery = false;
1266 failureRecoveryAttempts++;
1267 ce(LOW);
1268 return -1;
1269 }
1270 else {
1271 #endif
1272 errNotify();
1273 #if defined(FAILURE_HANDLING)
1274 }
1275 return 0;
1276 #else
1277 delay(100);
1278 #endif
1279 }
1280 }
1281 return 0;
1282}
1283
1284/******************************************************************/
1285
1286void RF24::errHandler()
1287{
1288
1289 #if defined(FAILURE_HANDLING)
1290 flush_tx();
1291 flush_rx();
1292 if (!failureFlushed) {
1293 failureFlushed = true;
1294 failureRecoveryAttempts++;
1295 }
1296 else {
1297 #endif
1298 errNotify();
1299 #if defined(FAILURE_HANDLING)
1300 failureFlushed = false;
1301 }
1302 ce(LOW);
1303 #endif
1304}
1305
1306#endif
1307
1308/******************************************************************/
1309
1310//Similar to the previous write, clears the interrupt flags
1311bool RF24::write(const void* buf, uint8_t len, const bool multicast)
1312{
1313
1314 //Start Writing
1315#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1316 bool doRecovery = true;
1317 do {
1318#endif
1319 startFastWrite(buf, len, multicast);
1320#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1321 } while (errHandler(&doRecovery) < 0);
1322#endif
1323
1324 ce(LOW);
1325
1326 write_register(nRF24L01::STATUS, RF24_IRQ_ALL);
1327
1328 //Max retries exceeded
1329 if (status & RF24_TX_DF) {
1330 flush_tx(); // Only going to be 1 packet in the FIFO at a time using this method, so just flush
1331 return 0;
1332 }
1333 //TX OK 1 or 0
1334 return 1;
1335}
1336
1337/****************************************************************************/
1338
1339bool RF24::write(const void* buf, uint8_t len)
1340{
1341 return write(buf, len, 0);
1342}
1343
1344/****************************************************************************/
1345
1346//For general use, the interrupt flags are not important to clear
1347bool RF24::writeBlocking(const void* buf, uint8_t len, uint32_t timeout)
1348{
1349 //Block until the FIFO is NOT full.
1350 //Keep track of the MAX retries and set auto-retry if seeing failures
1351 //This way the FIFO will fill up and allow blocking until packets go through
1352 //The radio will auto-clear everything in the FIFO as long as CE remains high
1353#if defined(FAILURE_HANDLING)
1354 bool timeoutInvoked = false;
1355#endif
1356
1357 uint32_t timer = millis(); // Get the time that the payload transmission started
1358
1359 while (update() & _BV(nRF24L01::TX_FULL)) { // Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
1360
1361 if (status & RF24_TX_DF) { // If MAX Retries have been reached
1362 reUseTX(); // Set re-transmit and clear the MAX_RT interrupt flag
1363 if (millis() - timer > timeout) {
1364#if defined(FAILURE_HANDLING)
1365 failureFlushed = false;
1366#endif
1367 return 0; // If this payload has exceeded the user-defined timeout, exit and return 0
1368 }
1369 }
1370#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1371 if (millis() - timer > (timeout + 95)) {
1372 errHandler();
1373 #if defined(FAILURE_HANDLING)
1374 timeoutInvoked = true;
1375 if (!failureFlushed) {
1376 #endif
1377 return 0;
1378 #if defined(FAILURE_HANDLING)
1379 }
1380 #endif
1381 }
1382#endif
1383 }
1384
1385 //Start Writing
1386 startFastWrite(buf, len, 0); // Write the payload if a buffer is clear
1387#if defined(FAILURE_HANDLING)
1388 if (!timeoutInvoked) {
1389 failureFlushed = false;
1390 }
1391#endif
1392 return 1; // Return 1 to indicate successful transmission
1393}
1394
1395/****************************************************************************/
1396
1397void RF24::reUseTX()
1398{
1399 ce(LOW);
1400 write_register(nRF24L01::STATUS, RF24_TX_DF); //Clear max retry flag
1401 read_register(nRF24L01::REUSE_TX_PL, (uint8_t*)nullptr, 0);
1402 IF_RF24_DEBUG(printf_P("[Reusing payload in TX FIFO]"););
1403 ce(HIGH); //Re-Transfer packet
1404}
1405
1406/****************************************************************************/
1407
1408bool RF24::writeFast(const void* buf, uint8_t len, const bool multicast)
1409{
1410 //Block until the FIFO is NOT full.
1411 //Keep track of the MAX retries and set auto-retry if seeing failures
1412 //Return 0 so the user can control the retries and set a timer or failure counter if required
1413 //The radio will auto-clear everything in the FIFO as long as CE remains high
1414
1415#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1416 uint32_t timer = millis();
1417 bool timeoutInvoked = false;
1418#endif
1419
1420 //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
1421 while (update() & _BV(nRF24L01::TX_FULL)) {
1422 if (status & RF24_TX_DF) {
1423#if defined(FAILURE_HANDLING)
1424 failureFlushed = false;
1425#endif
1426 return 0; //Return 0. The previous payload has not been retransmitted
1427 // From the user perspective, if you get a 0, call txStandBy()
1428 }
1429#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1430 if (millis() - timer > 95) {
1431 timeoutInvoked = true;
1432 errHandler();
1433 #if defined(FAILURE_HANDLING)
1434 if (!failureFlushed) {
1435 #endif
1436 return 0;
1437 #if defined(FAILURE_HANDLING)
1438 }
1439 #endif
1440 }
1441#endif
1442 }
1443 startFastWrite(buf, len, multicast); // Start Writing
1444#if defined(FAILURE_HANDLING)
1445 if (!timeoutInvoked) {
1446 failureFlushed = false;
1447 }
1448#endif
1449 return 1;
1450}
1451
1452bool RF24::writeFast(const void* buf, uint8_t len)
1453{
1454 return writeFast(buf, len, 0);
1455}
1456
1457/****************************************************************************/
1458
1459//Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
1460//In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
1461//Otherwise we enter Standby-II mode, which is still faster than standby mode
1462//Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
1463
1464void RF24::startFastWrite(const void* buf, uint8_t len, const bool multicast, bool startTx)
1465{ //TMRh20
1466
1467 write_payload(buf, len, multicast ? nRF24L01::W_TX_PAYLOAD_NO_ACK : nRF24L01::W_TX_PAYLOAD);
1468 if (startTx) {
1469 ce(HIGH);
1470 }
1471}
1472
1473/****************************************************************************/
1474
1475//Added the original startWrite back in so users can still use interrupts, ack payloads, etc
1476//Allows the library to pass all tests
1477bool RF24::startWrite(const void* buf, uint8_t len, const bool multicast)
1478{
1479
1480 // Send the payload
1481 write_payload(buf, len, multicast ? nRF24L01::W_TX_PAYLOAD_NO_ACK : nRF24L01::W_TX_PAYLOAD);
1482 ce(HIGH);
1483#if !defined(F_CPU) || F_CPU > 20000000
1484 delayMicroseconds(10);
1485#endif
1486#ifdef ARDUINO_ARCH_STM32
1487 if (F_CPU > 20000000) {
1488 delayMicroseconds(10);
1489 }
1490#endif
1491 ce(LOW);
1492 return !(status & _BV(nRF24L01::TX_FULL));
1493}
1494
1495/****************************************************************************/
1496
1497bool RF24::rxFifoFull()
1498{
1499 return read_register(nRF24L01::FIFO_STATUS) & _BV(nRF24L01::RX_FULL);
1500}
1501
1502/****************************************************************************/
1503
1504rf24_fifo_state_e RF24::isFifo(bool about_tx)
1505{
1506 uint8_t state = (read_register(nRF24L01::FIFO_STATUS) >> (4 * about_tx)) & 3;
1507 return static_cast<rf24_fifo_state_e>(state);
1508}
1509
1510/****************************************************************************/
1511
1512bool RF24::isFifo(bool about_tx, bool check_empty)
1513{
1514 return static_cast<bool>(static_cast<uint8_t>(isFifo(about_tx)) & _BV(!check_empty));
1515}
1516
1517/****************************************************************************/
1518
1519bool RF24::txStandBy()
1520{
1521
1522#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1523 uint32_t timeout = millis();
1524#endif
1525 while (!(read_register(nRF24L01::FIFO_STATUS) & _BV(nRF24L01::TX_EMPTY))) {
1526 if (status & RF24_TX_DF) {
1527 write_register(nRF24L01::STATUS, RF24_TX_DF);
1528 ce(LOW);
1529 flush_tx(); //Non blocking, flush the data
1530#if defined(FAILURE_HANDLING)
1531 failureFlushed = false;
1532#endif
1533 return 0;
1534 }
1535#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1536 if (millis() - timeout > 95) {
1537 errHandler();
1538 return 0;
1539 }
1540#endif
1541 }
1542
1543 ce(LOW); //Set STANDBY-I mode
1544#if defined(FAILURE_HANDLING)
1545 failureFlushed = false;
1546#endif
1547 return 1;
1548}
1549
1550/****************************************************************************/
1551
1552bool RF24::txStandBy(uint32_t timeout, bool startTx)
1553{
1554
1555 if (startTx) {
1556 stopListening();
1557 ce(HIGH);
1558 }
1559 uint32_t start = millis();
1560
1561 while (!(read_register(nRF24L01::FIFO_STATUS) & _BV(nRF24L01::TX_EMPTY))) {
1562 if (status & RF24_TX_DF) {
1563 write_register(nRF24L01::STATUS, RF24_TX_DF);
1564 ce(LOW); // Set re-transmit
1565 ce(HIGH);
1566 if (millis() - start >= timeout) {
1567 ce(LOW);
1568 flush_tx();
1569#if defined(FAILURE_HANDLING)
1570 failureFlushed = false;
1571#endif
1572 return 0;
1573 }
1574 }
1575#if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1576 if (millis() - start > timeout + 95) {
1577 errHandler();
1578 return 0;
1579 }
1580#endif
1581 }
1582
1583 ce(LOW); //Set STANDBY-I mode
1584#if defined(FAILURE_HANDLING)
1585 failureFlushed = false;
1586#endif
1587 return 1;
1588}
1589
1590/****************************************************************************/
1591
1592void RF24::maskIRQ(bool tx, bool fail, bool rx)
1593{
1594 /* clear the interrupt flags */
1595 config_reg = static_cast<uint8_t>(config_reg & ~(1 << nRF24L01::MASK_MAX_RT | 1 << nRF24L01::MASK_TX_DS | 1 << nRF24L01::MASK_RX_DR));
1596 /* set the specified interrupt flags */
1597 config_reg = static_cast<uint8_t>(config_reg | fail << nRF24L01::MASK_MAX_RT | tx << nRF24L01::MASK_TX_DS | rx << nRF24L01::MASK_RX_DR);
1598 write_register(nRF24L01::CONFIG, config_reg);
1599}
1600
1601/****************************************************************************/
1602
1603uint8_t RF24::getDynamicPayloadSize(void)
1604{
1605 uint8_t result = read_register(nRF24L01::R_RX_PL_WID);
1606
1607 if (result > 32 || !result) {
1608 flush_rx();
1609 return 0;
1610 }
1611 return result;
1612}
1613
1614/****************************************************************************/
1615
1616bool RF24::available(void)
1617{
1618 return (read_register(nRF24L01::FIFO_STATUS) & 1) == 0;
1619}
1620
1621/****************************************************************************/
1622
1623bool RF24::available(uint8_t* pipe_num)
1624{
1625 if (available()) { // if RX FIFO is not empty
1626 *pipe_num = (update() >> nRF24L01::RX_P_NO) & 0x07;
1627 return 1;
1628 }
1629 return 0;
1630}
1631
1632/****************************************************************************/
1633
1634void RF24::read(void* buf, uint8_t len)
1635{
1636
1637 // Fetch the payload
1638 read_payload(buf, len);
1639
1640 //Clear the only applicable interrupt flags
1641 write_register(nRF24L01::STATUS, RF24_RX_DR);
1642}
1643
1644/****************************************************************************/
1645
1646void RF24::whatHappened(bool& tx_ok, bool& tx_fail, bool& rx_ready)
1647{
1648 // Read the status & reset the status in one easy call
1649 // Or is that such a good idea?
1650 write_register(nRF24L01::STATUS, RF24_IRQ_ALL);
1651
1652 // Report to the user what happened
1653 tx_ok = status & RF24_TX_DS;
1654 tx_fail = status & RF24_TX_DF;
1655 rx_ready = status & RF24_RX_DR;
1656}
1657
1658/****************************************************************************/
1659
1660uint8_t RF24::clearStatusFlags(uint8_t flags)
1661{
1662 write_register(nRF24L01::STATUS, flags & RF24_IRQ_ALL);
1663 return status;
1664}
1665
1666/****************************************************************************/
1667
1668void RF24::setStatusFlags(uint8_t flags)
1669{
1670 // flip the `flags` to translate from "human understanding"
1671 config_reg = (config_reg & ~RF24_IRQ_ALL) | (~flags & RF24_IRQ_ALL);
1672 write_register(nRF24L01::CONFIG, config_reg);
1673}
1674
1675/****************************************************************************/
1676
1677uint8_t RF24::getStatusFlags()
1678{
1679 return status;
1680}
1681
1682/****************************************************************************/
1683
1684uint8_t RF24::update()
1685{
1686 read_register(nRF24L01::NOP, (uint8_t*)nullptr, 0);
1687 return status;
1688}
1689
1690/****************************************************************************/
1691
1692void RF24::openWritingPipe(uint64_t value)
1693{
1694 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1695 // expects it LSB first too, so we're good.
1696
1697 write_register(nRF24L01::RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
1698 write_register(nRF24L01::TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
1699 memcpy(pipe0_writing_address, &value, addr_width);
1700}
1701
1702/****************************************************************************/
1703
1704void RF24::openWritingPipe(const uint8_t* address)
1705{
1706 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1707 // expects it LSB first too, so we're good.
1708 write_register(nRF24L01::RX_ADDR_P0, address, addr_width);
1709 write_register(nRF24L01::TX_ADDR, address, addr_width);
1710 memcpy(pipe0_writing_address, address, addr_width);
1711}
1712
1713/****************************************************************************/
1714
1715static const PROGMEM uint8_t child_pipe[] = {nRF24L01::RX_ADDR_P0, nRF24L01::RX_ADDR_P1, nRF24L01::RX_ADDR_P2,
1716 nRF24L01::RX_ADDR_P3, nRF24L01::RX_ADDR_P4, nRF24L01::RX_ADDR_P5};
1717
1718void RF24::openReadingPipe(uint8_t child, uint64_t address)
1719{
1720 // If this is pipe 0, cache the address. This is needed because
1721 // openWritingPipe() will overwrite the pipe 0 address, so
1722 // startListening() will have to restore it.
1723 if (child == 0) {
1724 memcpy(pipe0_reading_address, &address, addr_width);
1725 _is_p0_rx = true;
1726 }
1727
1728 if (child <= 5) {
1729 // For pipes 2-5, only write the LSB
1730 if (child > 1) {
1731 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
1732 }
1733 // avoid overwriting the TX address on pipe 0 while still in TX mode.
1734 // NOTE, the cached RX address on pipe 0 is written when startListening() is called.
1735 else if (static_cast<bool>(config_reg & _BV(nRF24L01::PRIM_RX)) || child != 0) {
1736 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
1737 }
1738
1739 // Note it would be more efficient to set all of the bits for all open
1740 // pipes at once. However, I thought it would make the calling code
1741 // more simple to do it this way.
1742 write_register(nRF24L01::EN_RXADDR, static_cast<uint8_t>(read_register(nRF24L01::EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))));
1743 }
1744}
1745
1746/****************************************************************************/
1747
1748void RF24::setAddressWidth(uint8_t a_width)
1749{
1750 a_width = static_cast<uint8_t>(a_width - 2);
1751 if (a_width) {
1752 write_register(nRF24L01::SETUP_AW, static_cast<uint8_t>(a_width % 4));
1753 addr_width = static_cast<uint8_t>((a_width % 4) + 2);
1754 }
1755 else {
1756 write_register(nRF24L01::SETUP_AW, static_cast<uint8_t>(0));
1757 addr_width = static_cast<uint8_t>(2);
1758 }
1759}
1760
1761/****************************************************************************/
1762
1763void RF24::openReadingPipe(uint8_t child, const uint8_t* address)
1764{
1765 // If this is pipe 0, cache the address. This is needed because
1766 // openWritingPipe() will overwrite the pipe 0 address, so
1767 // startListening() will have to restore it.
1768 if (child == 0) {
1769 memcpy(pipe0_reading_address, address, addr_width);
1770 _is_p0_rx = true;
1771 }
1772 if (child <= 5) {
1773 // For pipes 2-5, only write the LSB
1774 if (child > 1) {
1775 write_register(pgm_read_byte(&child_pipe[child]), address, 1);
1776 }
1777 // avoid overwriting the TX address on pipe 0 while still in TX mode.
1778 // NOTE, the cached RX address on pipe 0 is written when startListening() is called.
1779 else if (static_cast<bool>(config_reg & _BV(nRF24L01::PRIM_RX)) || child != 0) {
1780 write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
1781 }
1782
1783 // Note it would be more efficient to set all of the bits for all open
1784 // pipes at once. However, I thought it would make the calling code
1785 // more simple to do it this way.
1786 write_register(nRF24L01::EN_RXADDR, static_cast<uint8_t>(read_register(nRF24L01::EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))));
1787 }
1788}
1789
1790/****************************************************************************/
1791
1792void RF24::closeReadingPipe(uint8_t pipe)
1793{
1794 write_register(nRF24L01::EN_RXADDR, static_cast<uint8_t>(read_register(nRF24L01::EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe]))));
1795 if (!pipe) {
1796 // keep track of pipe 0's RX state to avoid null vs 0 in addr cache
1797 _is_p0_rx = false;
1798 }
1799}
1800
1801/****************************************************************************/
1802
1803void RF24::toggle_features(void)
1804{
1805 beginTransaction();
1806#if defined(RF24_SPI_PTR)
1807 status = _spi->transfer(nRF24L01::ACTIVATE);
1808 _spi->transfer(0x73);
1809#else
1810 status = _SPI.transfer(nRF24L01::ACTIVATE);
1811 _SPI.transfer(0x73);
1812#endif
1813 endTransaction();
1814}
1815
1816/****************************************************************************/
1817
1818void RF24::enableDynamicPayloads(void)
1819{
1820 // Enable dynamic payload throughout the system
1821
1822 //toggle_features();
1823 write_register(nRF24L01::FEATURE, read_register(nRF24L01::FEATURE) | _BV(nRF24L01::EN_DPL));
1824
1825 IF_RF24_DEBUG(printf_P("FEATURE=%i\r\n", read_register(nRF24L01::FEATURE)));
1826
1827 // Enable dynamic payload on all pipes
1828 //
1829 // Not sure the use case of only having dynamic payload on certain
1830 // pipes, so the library does not support it.
1831 write_register(nRF24L01::DYNPD, read_register(nRF24L01::DYNPD) | _BV(nRF24L01::DPL_P5) | _BV(nRF24L01::DPL_P4) | _BV(nRF24L01::DPL_P3) | _BV(nRF24L01::DPL_P2) | _BV(nRF24L01::DPL_P1) | _BV(nRF24L01::DPL_P0));
1832
1833 dynamic_payloads_enabled = true;
1834}
1835
1836/****************************************************************************/
1837
1838void RF24::disableDynamicPayloads(void)
1839{
1840 // Disables dynamic payload throughout the system. Also disables Ack Payloads
1841
1842 //toggle_features();
1843 write_register(nRF24L01::FEATURE, 0);
1844
1845 IF_RF24_DEBUG(printf_P("FEATURE=%i\r\n", read_register(nRF24L01::FEATURE)));
1846
1847 // Disable dynamic payload on all pipes
1848 //
1849 // Not sure the use case of only having dynamic payload on certain
1850 // pipes, so the library does not support it.
1851 write_register(nRF24L01::DYNPD, 0);
1852
1853 dynamic_payloads_enabled = false;
1854 ack_payloads_enabled = false;
1855}
1856
1857/****************************************************************************/
1858
1859void RF24::enableAckPayload(void)
1860{
1861 // enable ack payloads and dynamic payload features
1862
1863 if (!ack_payloads_enabled) {
1864 write_register(nRF24L01::FEATURE, read_register(nRF24L01::FEATURE) | _BV(nRF24L01::EN_ACK_PAY) | _BV(nRF24L01::EN_DPL));
1865
1866 IF_RF24_DEBUG(printf_P("FEATURE=%i\r\n", read_register(nRF24L01::FEATURE)));
1867
1868 // Enable dynamic payload on pipes 0 & 1
1869 write_register(nRF24L01::DYNPD, read_register(nRF24L01::DYNPD) | _BV(nRF24L01::DPL_P1) | _BV(nRF24L01::DPL_P0));
1870 dynamic_payloads_enabled = true;
1871 ack_payloads_enabled = true;
1872 }
1873}
1874
1875/****************************************************************************/
1876
1877void RF24::disableAckPayload(void)
1878{
1879 // disable ack payloads (leave dynamic payload features as is)
1880 if (ack_payloads_enabled) {
1881 write_register(nRF24L01::FEATURE, static_cast<uint8_t>(read_register(nRF24L01::FEATURE) & ~_BV(nRF24L01::EN_ACK_PAY)));
1882
1883 IF_RF24_DEBUG(printf_P("FEATURE=%i\r\n", read_register(nRF24L01::FEATURE)));
1884
1885 ack_payloads_enabled = false;
1886 }
1887}
1888
1889/****************************************************************************/
1890
1891void RF24::enableDynamicAck(void)
1892{
1893 //
1894 // enable dynamic ack features
1895 //
1896 //toggle_features();
1897 write_register(nRF24L01::FEATURE, read_register(nRF24L01::FEATURE) | _BV(nRF24L01::EN_DYN_ACK));
1898
1899 IF_RF24_DEBUG(printf_P("FEATURE=%i\r\n", read_register(nRF24L01::FEATURE)));
1900}
1901
1902/****************************************************************************/
1903
1904bool RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
1905{
1906 if (ack_payloads_enabled) {
1907 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
1908
1909 write_register(nRF24L01::W_ACK_PAYLOAD | (pipe & 0x07), current, rf24_min(len, static_cast<uint8_t>(32)));
1910 return !(status & _BV(nRF24L01::TX_FULL));
1911 }
1912 return 0;
1913}
1914
1915/****************************************************************************/
1916
1917bool RF24::isAckPayloadAvailable(void)
1918{
1919 return available();
1920}
1921
1922/****************************************************************************/
1923
1924bool RF24::isPVariant(void)
1925{
1926 return _is_p_variant;
1927}
1928
1929/****************************************************************************/
1930
1931void RF24::setAutoAck(bool enable)
1932{
1933 if (enable) {
1934 write_register(nRF24L01::EN_AA, 0x3F);
1935 }
1936 else {
1937 write_register(nRF24L01::EN_AA, 0);
1938 // accommodate ACK payloads feature
1939 if (ack_payloads_enabled) {
1940 disableAckPayload();
1941 }
1942 }
1943}
1944
1945/****************************************************************************/
1946
1947void RF24::setAutoAck(uint8_t pipe, bool enable)
1948{
1949 if (pipe < 6) {
1950 uint8_t en_aa = read_register(nRF24L01::EN_AA);
1951 if (enable) {
1952 en_aa |= static_cast<uint8_t>(_BV(pipe));
1953 }
1954 else {
1955 en_aa = static_cast<uint8_t>(en_aa & ~_BV(pipe));
1956 if (ack_payloads_enabled && !pipe) {
1957 disableAckPayload();
1958 }
1959 }
1960 write_register(nRF24L01::EN_AA, en_aa);
1961 }
1962}
1963
1964/****************************************************************************/
1965
1966bool RF24::testCarrier(void)
1967{
1968 return (read_register(nRF24L01::CD) & 1);
1969}
1970
1971/****************************************************************************/
1972
1973bool RF24::testRPD(void)
1974{
1975 return (read_register(nRF24L01::RPD) & 1);
1976}
1977
1978/****************************************************************************/
1979
1980void RF24::setPALevel(uint8_t level, bool lnaEnable)
1981{
1982 uint8_t setup = read_register(nRF24L01::RF_SETUP) & static_cast<uint8_t>(0xF8);
1983 setup |= _pa_level_reg_value(level, lnaEnable);
1984 write_register(nRF24L01::RF_SETUP, setup);
1985}
1986
1987/****************************************************************************/
1988
1989uint8_t RF24::getPALevel(void)
1990{
1991 return (read_register(nRF24L01::RF_SETUP) & (_BV(nRF24L01::RF_PWR_LOW) | _BV(nRF24L01::RF_PWR_HIGH))) >> 1;
1992}
1993
1994/****************************************************************************/
1995
1996uint8_t RF24::getARC(void)
1997{
1998 return read_register(nRF24L01::OBSERVE_TX) & 0x0F;
1999}
2000
2001/****************************************************************************/
2002
2003bool RF24::setDataRate(rf24_datarate_e speed)
2004{
2005 bool result = false;
2006 uint8_t setup = read_register(nRF24L01::RF_SETUP);
2007
2008 // HIGH and LOW '00' is 1Mbs - our default
2009 setup = static_cast<uint8_t>(setup & ~(_BV(nRF24L01::RF_DR_LOW) | _BV(nRF24L01::RF_DR_HIGH)));
2010 setup |= _data_rate_reg_value(speed);
2011
2012 write_register(nRF24L01::RF_SETUP, setup);
2013
2014 // Verify our result
2015 if (read_register(nRF24L01::RF_SETUP) == setup) {
2016 result = true;
2017 }
2018 return result;
2019}
2020
2021/****************************************************************************/
2022
2023rf24_datarate_e RF24::getDataRate(void)
2024{
2025 rf24_datarate_e result;
2026 uint8_t dr = read_register(nRF24L01::RF_SETUP) & (_BV(nRF24L01::RF_DR_LOW) | _BV(nRF24L01::RF_DR_HIGH));
2027
2028 // switch uses RAM (evil!)
2029 // Order matters in our case below
2030 if (dr == _BV(nRF24L01::RF_DR_LOW)) {
2031 // '10' = 250KBPS
2032 result = RF24_250KBPS;
2033 }
2034 else if (dr == _BV(nRF24L01::RF_DR_HIGH)) {
2035 // '01' = 2MBPS
2036 result = RF24_2MBPS;
2037 }
2038 else {
2039 // '00' = 1MBPS
2040 result = RF24_1MBPS;
2041 }
2042 return result;
2043}
2044
2045/****************************************************************************/
2046
2047void RF24::setCRCLength(rf24_crclength_e length)
2048{
2049 config_reg = static_cast<uint8_t>(config_reg & ~(_BV(nRF24L01::CRCO) | _BV(nRF24L01::EN_CRC)));
2050
2051 // switch uses RAM (evil!)
2052 if (length == RF24_CRC_DISABLED) {
2053 // Do nothing, we turned it off above.
2054 }
2055 else if (length == RF24_CRC_8) {
2056 config_reg |= _BV(nRF24L01::EN_CRC);
2057 }
2058 else {
2059 config_reg |= _BV(nRF24L01::EN_CRC);
2060 config_reg |= _BV(nRF24L01::CRCO);
2061 }
2062 write_register(nRF24L01::CONFIG, config_reg);
2063}
2064
2065/****************************************************************************/
2066
2067rf24_crclength_e RF24::getCRCLength(void)
2068{
2069 rf24_crclength_e result = RF24_CRC_DISABLED;
2070 uint8_t AA = read_register(nRF24L01::EN_AA);
2071 config_reg = read_register(nRF24L01::CONFIG);
2072
2073 if (config_reg & _BV(nRF24L01::EN_CRC) || AA) {
2074 if (config_reg & _BV(nRF24L01::CRCO)) {
2075 result = RF24_CRC_16;
2076 }
2077 else {
2078 result = RF24_CRC_8;
2079 }
2080 }
2081
2082 return result;
2083}
2084
2085/****************************************************************************/
2086
2087void RF24::disableCRC(void)
2088{
2089 config_reg = static_cast<uint8_t>(config_reg & ~_BV(nRF24L01::EN_CRC));
2090 write_register(nRF24L01::CONFIG, config_reg);
2091}
2092
2093/****************************************************************************/
2094void RF24::setRetries(uint8_t delay, uint8_t count)
2095{
2096 write_register(nRF24L01::SETUP_RETR, static_cast<uint8_t>(rf24_min(15, delay) << nRF24L01::ARD | rf24_min(15, count)));
2097}
2098
2099/****************************************************************************/
2100void RF24::startConstCarrier(rf24_pa_dbm_e level, uint8_t channel)
2101{
2102 stopListening();
2103 write_register(nRF24L01::RF_SETUP, read_register(nRF24L01::RF_SETUP) | _BV(nRF24L01::CONT_WAVE) | _BV(nRF24L01::PLL_LOCK));
2104 if (isPVariant()) {
2105 setAutoAck(0);
2106 setRetries(0, 0);
2107 uint8_t dummy_buf[32];
2108 for (uint8_t i = 0; i < 32; ++i)
2109 dummy_buf[i] = 0xFF;
2110
2111 // use write_register() instead of openWritingPipe() to bypass
2112 // truncation of the address with the current RF24::addr_width value
2113 write_register(nRF24L01::TX_ADDR, reinterpret_cast<uint8_t*>(&dummy_buf), 5);
2114 flush_tx(); // so we can write to top level
2115
2116 // use write_register() instead of write_payload() to bypass
2117 // truncation of the payload with the current RF24::payload_size value
2118 write_register(nRF24L01::W_TX_PAYLOAD, reinterpret_cast<const uint8_t*>(&dummy_buf), 32);
2119
2120 disableCRC();
2121 }
2122 setPALevel(level);
2123 setChannel(channel);
2124 IF_RF24_DEBUG(printf_P(PSTR("RF_SETUP=%02x\r\n"), read_register(nRF24L01::RF_SETUP)));
2125 ce(HIGH);
2126 if (isPVariant()) {
2127 delay(1); // datasheet says 1 ms is ok in this instance
2128 reUseTX(); // CE gets toggled here
2129 }
2130}
2131
2132/****************************************************************************/
2133
2134void RF24::stopConstCarrier()
2135{
2136 /*
2137 * A note from the datasheet:
2138 * Do not use REUSE_TX_PL together with CONT_WAVE=1. When both these
2139 * registers are set the chip does not react when setting CE low. If
2140 * however, both registers are set PWR_UP = 0 will turn TX mode off.
2141 */
2142 powerDown(); // per datasheet recommendation (just to be safe)
2143 write_register(nRF24L01::RF_SETUP, static_cast<uint8_t>(read_register(nRF24L01::RF_SETUP) & ~_BV(nRF24L01::CONT_WAVE) & ~_BV(nRF24L01::PLL_LOCK)));
2144 ce(LOW);
2145 flush_tx();
2146 if (isPVariant()) {
2147 // restore the cached TX address
2148 write_register(nRF24L01::TX_ADDR, pipe0_writing_address, addr_width);
2149 }
2150}
2151
2152/****************************************************************************/
2153
2154void RF24::toggleAllPipes(bool isEnabled)
2155{
2156 write_register(nRF24L01::EN_RXADDR, static_cast<uint8_t>(isEnabled ? 0x3F : 0));
2157}
2158
2159/****************************************************************************/
2160
2161uint8_t RF24::_data_rate_reg_value(rf24_datarate_e speed)
2162{
2163#if !defined(F_CPU) || F_CPU > 20000000
2164 txDelay = 280;
2165#else //16Mhz Arduino
2166 txDelay = 85;
2167#endif
2168 if (speed == RF24_250KBPS) {
2169#if !defined(F_CPU) || F_CPU > 20000000
2170 txDelay = 505;
2171#else //16Mhz Arduino
2172 txDelay = 155;
2173#endif
2174 // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
2175 // Making it '10'.
2176 return static_cast<uint8_t>(_BV(nRF24L01::RF_DR_LOW));
2177 }
2178 else if (speed == RF24_2MBPS) {
2179#if !defined(F_CPU) || F_CPU > 20000000
2180 txDelay = 240;
2181#else // 16Mhz Arduino
2182 txDelay = 65;
2183#endif
2184 // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
2185 // Making it '01'
2186 return static_cast<uint8_t>(_BV(nRF24L01::RF_DR_HIGH));
2187 }
2188 // HIGH and LOW '00' is 1Mbs - our default
2189 return static_cast<uint8_t>(0);
2190}
2191
2192/****************************************************************************/
2193
2194uint8_t RF24::_pa_level_reg_value(uint8_t level, bool lnaEnable)
2195{
2196 // If invalid level, go to max PA
2197 // Else set level as requested
2198 // + lnaEnable (1 or 0) to support the SI24R1 chip extra bit
2199 return static_cast<uint8_t>(((level > RF24_PA_MAX ? static_cast<uint8_t>(RF24_PA_MAX) : level) << 1) + lnaEnable);
2200}
2201
2202/****************************************************************************/
2203
2204void RF24::setRadiation(uint8_t level, rf24_datarate_e speed, bool lnaEnable)
2205{
2206 uint8_t setup = _data_rate_reg_value(speed);
2207 setup |= _pa_level_reg_value(level, lnaEnable);
2208 write_register(nRF24L01::RF_SETUP, setup);
2209}