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authorkrolxon <krolyxon@tutanota.com>2026-01-05 12:12:57 +0530
committerkrolxon <krolyxon@tutanota.com>2026-01-05 12:12:57 +0530
commit8d479202b0c9dbe13bb95ad572a060b69642ec26 (patch)
tree5a8f8c015c47bef497e4a54808da667db857fbfd /src/cpu.rs
parent2fb5bbaa8d97a390b3175026040709c762cb93ec (diff)
add labels, improve documentation, add step debug
Diffstat (limited to 'src/cpu.rs')
-rw-r--r--src/cpu.rs18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu.rs b/src/cpu.rs
index 13d2fc8..df8b3a2 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -2,6 +2,7 @@ use crate::instructions::Instruction;
use crate::memory::Memory;
#[derive(Default, Debug)]
+#[allow(dead_code)]
pub struct CPU {
pub a: u8,
pub b: u8,
@@ -18,6 +19,23 @@ pub struct CPU {
}
impl CPU {
+
+ pub fn debug_instr(&self, mem: &Memory) {
+ let opcode = mem.read(self.pc);
+
+ println!(
+ "PC={:04X} {:<3} | A={:02X} B={:02X} C={:02X} D={:02X} | Z={} C={}",
+ self.pc,
+ Instruction::opcode_name(opcode),
+ self.a,
+ self.b,
+ self.c,
+ self.d,
+ self.zero as u8,
+ self.carry as u8
+ );
+ }
+
pub fn step(&mut self, mem: &mut Memory) {
let opcode = mem.read(self.pc);
self.inc_pc();