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bench51be61e5a

add jnz, README.md

Author
krolxon
Date
2026-01-04 19:10 +0530
Parent
2441729
Commit
be61e5ae6bca45a6dafc46cfe0957a8db96f9e4c

+27 −2

4 files changed

  1. A README.md +10 −0
  2. M src/cpu.rs +13 −0
  3. M src/instructions.rs +1 −0
  4. M src/main.rs +3 −2
A README.md View
@@ -0,0 +1,10 @@
1+# 8-Bit CPU Simulator
2+
3+## Added instructions
4+1. MOV
5+2. ADD
6+3. SUB
7+4. JMP (Jump)
8+5. JZ (Jump if zero)
9+5. JZ (Jump if not zero)
10+6. HLT (Halt)
M src/cpu.rs View
@@ -153,4 +153,17 @@ impl CPU {
153153
154154 }
155155
156+ pub fn jnz(&mut self, mem: &mut Memory) {
157+ let low = mem.read(self.pc) as u16; self.inc_pc();
158+ let high = mem.read(self.pc) as u16; self.inc_pc();
159+
160+ let addrs = (high << 8) | low;
161+
162+ if !self.zero {
163+ self.pc = addrs;
164+ }
165+
166+ }
167+
168+
156169 }
M src/instructions.rs View
@@ -5,5 +5,6 @@ pub enum Instruction {
55 SUB = 0x03,
66 JMP = 0x04,
77 JZ = 0x05,
8+ JNZ = 0x06,
89 HLT = 0xFF,
910 }
M src/main.rs View
@@ -20,7 +20,7 @@ fn main() {
2020 // b = 2
2121 mem.write(0x0003, Instruction::MOV as u8);
2222 mem.write(0x0004, 1);
23− mem.write(0x0005, 5);
23+ mem.write(0x0005, 3);
2424
2525 // a = a + b
2626 mem.write(0x0006, Instruction::SUB as u8);
@@ -28,7 +28,7 @@ fn main() {
2828 mem.write(0x0008, 1);
2929
3030 // JMP to halt
31− mem.write(0x0009, Instruction::JZ as u8);
31+ mem.write(0x0009, Instruction::JNZ as u8);
3232 mem.write(0x000a, 0x0f); // Low
3333 mem.write(0x000b, 0x00); // High
3434
@@ -50,6 +50,7 @@ fn main() {
5050 x if x == Instruction::SUB as u8 => cpu.sub(&mut mem),
5151 x if x == Instruction::JMP as u8 => cpu.jmp(&mut mem),
5252 x if x == Instruction::JZ as u8 => cpu.jz(&mut mem),
53+ x if x == Instruction::JNZ as u8 => cpu.jnz(&mut mem),
5354 x if x == Instruction::HLT as u8 => cpu.halt(),
5455 _ => panic!("Unknown opcode {:02X}", opcode),
5556 }