Krolyxon
Commit 4251847

Branches

Tags

Refs →

bench514251847

formatting

Author
krolxon
Date
2026-01-13 19:21 +0530
Parent
5d34df5
Commit
425184747c9c61311dfbcdaa125ba2e49f713414

+28 −32

4 files changed

Browse files Patch
−Context 3+
  1. M src/assembler.rs +4 −8
  2. M src/cpu.rs +17 −19
  3. M src/instructions.rs +1 −1
  4. M src/main.rs +6 −4
M src/assembler.rs View
@@ -75,7 +75,7 @@ pub fn assembler(source: &str) -> Vec<u8> {
7575 match tokens[0].as_str() {
7676 "mov" => {
7777 // mov reg, imm
78− let r1= parse_reg(&tokens[1]);
78+ let r1 = parse_reg(&tokens[1]);
7979 if is_reg(&tokens[2]) {
8080 let r2 = parse_reg(&tokens[2]);
8181 bytes.push(Instruction::MOV_RR as u8);
@@ -104,7 +104,6 @@ pub fn assembler(source: &str) -> Vec<u8> {
104104 bytes.push(r1);
105105 bytes.push(imm);
106106 }
107−
108107 }
109108
110109 "sub" => {
@@ -161,7 +160,6 @@ pub fn assembler(source: &str) -> Vec<u8> {
161160 bytes.push(Instruction::MUL as u8);
162161 bytes.push(r1);
163162 bytes.push(r2);
164−
165163 }
166164
167165 "div" => {
@@ -174,13 +172,11 @@ pub fn assembler(source: &str) -> Vec<u8> {
174172 }
175173
176174 "call" => {
177− let addr = *symbols
178− .get(&tokens[1])
179− .expect("Unknown label");
175+ let addr = *symbols.get(&tokens[1]).expect("Unknown label");
180176
181177 bytes.push(Instruction::CALL as u8);
182− bytes.push((addr & 0xFF) as u8); // low
183− bytes.push((addr >> 8) as u8); // high
178+ bytes.push((addr & 0xFF) as u8); // low
179+ bytes.push((addr >> 8) as u8); // high
184180 }
185181
186182 "ret" => {
M src/cpu.rs View
@@ -89,7 +89,6 @@ impl CPU {
8989 self.sp = self.sp.wrapping_sub(1);
9090 }
9191
92−
9392 pub fn halt(&mut self) {
9493 self.halted = true;
9594 }
@@ -114,7 +113,7 @@ impl CPU {
114113 pub fn mov_rr(&mut self, mem: &Memory) {
115114 let dest = mem.read(self.pc);
116115 self.inc_pc();
117− let src= mem.read(self.pc);
116+ let src = mem.read(self.pc);
118117 self.inc_pc();
119118
120119 let val = self.get_reg(src);
@@ -123,7 +122,6 @@ impl CPU {
123122 self.zero = val == 0;
124123 }
125124
126−
127125 pub fn add_rr(&mut self, mem: &Memory) {
128126 let dest = mem.read(self.pc);
129127 self.pc += 1;
@@ -166,7 +164,6 @@ impl CPU {
166164 self.carry = carry;
167165 }
168166 pub fn add_ri(&mut self, mem: &Memory) {
169−
170167 let dest = mem.read(self.pc);
171168 self.pc += 1;
172169 let imm = mem.read(self.pc);
@@ -192,7 +189,6 @@ impl CPU {
192189 self.carry = carry;
193190 }
194191
195−
196192 pub fn sub_rr(&mut self, mem: &Memory) {
197193 let dest = mem.read(self.pc);
198194 self.pc += 1;
@@ -235,7 +231,7 @@ impl CPU {
235231 self.carry = borrow;
236232 }
237233
238− pub fn sub_ri(&mut self, mem: &Memory) {
234+ pub fn sub_ri(&mut self, mem: &Memory) {
239235 let dest = mem.read(self.pc);
240236 self.pc += 1;
241237 let imm = mem.read(self.pc);
@@ -261,7 +257,6 @@ impl CPU {
261257 self.carry = borrow;
262258 }
263259
264−
265260 pub fn jmp(&mut self, mem: &Memory) {
266261 let low = mem.read(self.pc) as u16;
267262 self.inc_pc();
@@ -329,24 +324,28 @@ impl CPU {
329324 }
330325
331326 pub fn mul(&mut self, mem: &Memory) {
332− let dest = mem.read(self.pc); self.inc_pc();
333− let src = mem.read(self.pc); self.inc_pc();
327+ let dest = mem.read(self.pc);
328+ self.inc_pc();
329+ let src = mem.read(self.pc);
330+ self.inc_pc();
334331
335332 let lhs = self.get_reg(dest);
336333 let rhs = self.get_reg(src);
337334
338335 let result16 = (lhs as u16) * (rhs as u16);
339− let result8 = (result16 & 0xFF) as u8;
336+ let result8 = (result16 & 0xFF) as u8;
340337
341338 self.set_reg(dest, result8);
342339
343− self.zero = result8 == 0;
340+ self.zero = result8 == 0;
344341 self.carry = result16 > 0xFF;
345342 }
346343
347344 pub fn div(&mut self, mem: &Memory) {
348− let dest = mem.read(self.pc); self.inc_pc();
349− let src = mem.read(self.pc); self.inc_pc();
345+ let dest = mem.read(self.pc);
346+ self.inc_pc();
347+ let src = mem.read(self.pc);
348+ self.inc_pc();
350349
351350 let lhs = self.get_reg(dest);
352351 let rhs = self.get_reg(src);
@@ -365,16 +364,17 @@ impl CPU {
365364 // carry unchanged
366365 }
367366
368− pub fn call(&mut self, mem: &mut Memory ) {
369− let low = mem.read(self.pc) as u16; self.inc_pc();
370− let high = mem.read(self.pc) as u16; self.inc_pc();
367+ pub fn call(&mut self, mem: &mut Memory) {
368+ let low = mem.read(self.pc) as u16;
369+ self.inc_pc();
370+ let high = mem.read(self.pc) as u16;
371+ self.inc_pc();
371372 let addr = (high << 8) | low;
372373
373374 let return_addr = self.pc;
374375
375376 self.push16(mem, return_addr);
376377 self.pc = addr;
377−
378378 }
379379
380380 pub fn ret(&mut self, mem: &mut Memory) {
@@ -382,7 +382,6 @@ impl CPU {
382382 self.pc = addr;
383383 }
384384
385−
386385 pub fn syscall(&mut self, mem: &Memory) {
387386 let num = mem.read(self.pc);
388387 self.pc = self.pc.wrapping_add(1);
@@ -422,5 +421,4 @@ impl CPU {
422421 _ => panic!("Invalid register"),
423422 }
424423 }
425−
426424 }
M src/instructions.rs View
@@ -21,7 +21,7 @@ pub enum Instruction {
2121 }
2222
2323 impl Instruction {
24− pub fn opcode_name(op: u8) -> &'static str{
24+ pub fn opcode_name(op: u8) -> &'static str {
2525 match op {
2626 0x01 | 0x08 => "MOV",
2727 0x02 | 0x0A => "ADD",
M src/main.rs View
@@ -5,10 +5,10 @@ mod memory;
55
66 use std::io;
77
8+use crate::assembler::assembler;
9+use clap::Parser;
810 use cpu::CPU;
911 use memory::Memory;
10−use clap::Parser;
11−use crate::assembler::assembler;
1212
1313 #[derive(Parser, Debug)]
1414 #[command(version, about, long_about = None)]
@@ -17,11 +17,13 @@ struct Args {
1717 filename: String,
1818 }
1919
20−
2120 fn main() {
2221 let args = Args::parse();
2322
24− let mut cpu = CPU {sp: 0xFFFE, ..Default::default( )};
23+ let mut cpu = CPU {
24+ sp: 0xFFFE,
25+ ..Default::default()
26+ };
2527 let mut mem = Memory::new();
2628
2729 let asm = std::fs::read_to_string(args.filename).unwrap();