Commit a921fe1

bench51a921fe1

rewrite as an 8051 TUI assembler, simulator and debugger

Replace the custom 8-bit ISA with an Intel 8051 toolchain and a
ratatui front end, in the spirit of a lightweight Keil uVision.

- isa: single opcode table (all 255 opcodes, sizes, cycles) shared by
  the assembler, disassembler and simulator
- asm: two-pass assembler with expressions, bit addressing, predefined
  SFR/bit names, ORG/DB/DW/DS/EQU/SET/BIT/DATA/... directives, Keil-style
  .lst listing and Intel HEX read/write; headless --assemble mode
- sim: full instruction set with CY/AC/OV/P flags and cycle counts,
  register banks, ports with latch/pin semantics, timers 0/1 (modes
  0-3), interrupts with two priority levels, UART modes 0-3 timed from
  timer 1, idle/power-down; disassembler
- ui: edit mode (editor, listing/HEX/errors tabs) and debug mode
  (source with PC, registers, peripherals, memory viewer, ports, serial
  terminal); run/pause, step into/over/out, run to cursor, breakpoints,
  memory poke; .hex files open as re-assemblable disassembly; Ctrl-G
  edits the source in $EDITOR and reloads on exit
- new examples and README; tests for encodings, flags, peripherals and
  the example programs

Author: krolyxon
Date: 2026-10-22 23:59 +0530
Parent: 4251847
Commit: a921fe164b81a6465da1f4941a192e483be30e85

+7506 −909

38 files changed

Browse files Patch

−Context 3+

M .gitignore +2 −0
M Cargo.lock +1695 −40
M Cargo.toml +4 −1
M README.md +94 −97
D examples/arithmetic.asm +0 −9
A examples/bcd_add.asm +21 −0
A examples/blink.asm +23 −0
A examples/button_int0.asm +20 −0
D examples/call.asm +0 −7
D examples/cmp.asm +0 −4
D examples/div.asm +0 −4
A examples/lookup_movc.asm +20 −0
D examples/loops.asm +0 −13
D examples/mul.asm +0 −4
A examples/serial_hello.asm +43 −0
D examples/syscall.asm +0 −7
D examples/table.asm +0 −9
A examples/timer_irq.asm +28 −0
A src/asm/expr.rs +251 −0
A src/asm/hex.rs +117 −0
A src/asm/lexer.rs +175 −0
A src/asm/listing.rs +53 −0
A src/asm/mod.rs +940 −0
D src/assembler.rs +0 −201
D src/cpu.rs +0 −424
D src/instructions.rs +0 −43
A src/isa.rs +347 −0
M src/main.rs +81 −29
D src/memory.rs +0 −17
A src/sfr.rs +146 −0
A src/sim/cpu.rs +528 −0
A src/sim/disasm.rs +91 −0
A src/sim/mod.rs +449 −0
A src/sim/periph.rs +403 −0
A src/ui/app.rs +903 −0
A src/ui/draw.rs +882 −0
A src/ui/mod.rs +68 −0
A src/ui/syntax.rs +122 −0

M .gitignore View

M Cargo.lock View

M Cargo.toml View

M README.md View

D examples/arithmetic.asm View

A examples/bcd_add.asm View

A examples/blink.asm View

A examples/button_int0.asm View

D examples/call.asm View

D examples/cmp.asm View

D examples/div.asm View

A examples/lookup_movc.asm View

D examples/loops.asm View

D examples/mul.asm View

A examples/serial_hello.asm View

D examples/syscall.asm View

D examples/table.asm View

A examples/timer_irq.asm View

A src/asm/expr.rs View

A src/asm/hex.rs View

A src/asm/lexer.rs View

A src/asm/listing.rs View

A src/asm/mod.rs View

D src/assembler.rs View

D src/cpu.rs View

D src/instructions.rs View

A src/isa.rs View

M src/main.rs View

D src/memory.rs View

A src/sfr.rs View

A src/sim/cpu.rs View

A src/sim/disasm.rs View

A src/sim/mod.rs View

A src/sim/periph.rs View

A src/ui/app.rs View

A src/ui/draw.rs View

A src/ui/mod.rs View

A src/ui/syntax.rs View

		@@ -1 +1,3 @@
1	1		/target
	2	+	examples/*.hex
	3	+	examples/*.lst

		@@ -1,7 +1,10 @@
1	1		[package]
2		−	name = "cpu-emulator"
	2	+	name = "i8051"
3	3		version = "0.1.0"
4	4		edition = "2024"
	5	+	description = "A TUI Intel 8051 assembler, simulator and debugger"
5	6
6	7		[dependencies]
7	8		clap = { version = "4.5.54", features = ["derive"] }
	9	+	ratatui = "0.30"
	10	+	ratatui-textarea = "0.9"

	@@ -1,9 +0,0 @@
1	−	; move imm 10 to register A
2	−	mov a, 10
3	−	; move imm 5 to register B
4	−	mov b, 5
5	−	; Add a & B
6	−	add a, 2
7	−	sub a, 2
8	−	; Halt
9	−	hlt

	@@ -0,0 +1,21 @@
1	+	; Packed BCD addition with DA A: 4-digit 1234 + 5678 = 6912.
2	+	; Watch A, CY and AC in the Registers panel while stepping.
3	+
4	+	ORG 0000h
5	+	MOV R0,#34h ; low byte of first number
6	+	MOV R1,#12h ; high byte
7	+	MOV R2,#78h ; low byte of second number
8	+	MOV R3,#56h ; high byte
9	+
10	+	MOV A,R0
11	+	ADD A,R2 ; 34h + 78h = ACh (binary)
12	+	DA A ; -> 12h, CY = 1
13	+	MOV 30h,A
14	+	MOV A,R1
15	+	ADDC A,R3 ; 12h + 56h + carry
16	+	DA A ; -> 69h
17	+	MOV 31h,A ; result 6912 in 31h:30h
18	+
19	+	SJMP $
20	+
21	+	END

	@@ -0,0 +1,23 @@
1	+	; Blink: toggle all of P1 with a software delay loop.
2	+	; Step with F11, or run with F5 and watch the Ports panel.
3	+
4	+	ORG 0000h
5	+	LJMP main
6	+
7	+	ORG 0030h
8	+	main: MOV P1,#0FFh
9	+	loop: CPL P1.0 ; toggle the LED on P1.0
10	+	MOV A,P1
11	+	CPL A
12	+	MOV P2,A ; P2 mirrors P1 inverted
13	+	ACALL delay
14	+	SJMP loop
15	+
16	+	; About 2 * 50 * 250 machine cycles.
17	+	delay: MOV R6,#50
18	+	d1: MOV R7,#250
19	+	d2: DJNZ R7,d2
20	+	DJNZ R6,d1
21	+	RET
22	+
23	+	END

		@@ -1,113 +1,110 @@
1		−	# 8-Bit CPU Emulator
	1	+	# i8051 — a TUI 8051 assembler, simulator & debugger
2	2
3		−	This project is an educational 8-bit CPU emulator written in Rust, it's build to understand core computer architecture concepts such as instruction sets, flags,
4		−	control flow, stacks and system calls.
	3	+	A small, Keil µVision-style IDE for the Intel 8051 that runs in your terminal.
	4	+	Write assembly in the built-in editor, assemble it, inspect the listing and
	5	+	Intel HEX output, then run, pause and single-step the program while watching
	6	+	registers, SFRs, memory, ports, timers, interrupts and the serial port.
5	7
6		−	This project is not a production CPU and not accurate. It is designed purely for learning and experimentation.
	8	+	Built in Rust with [ratatui](https://ratatui.rs). It is a learning tool, not a
	9	+	cycle-exact replacement for a vendor simulator.
7	10
8	11		-----
9	12
10	13		## Features
11	14
12		−	- Custom 8-bit ISA (control-flow and arithmetic operations)
13		−	- 4 general-purpose registers
14		−	- 64 KB (0x0000-0xFFFF) byte-addressable memory
15		−	- Two-pass assembler with label support
16		−	- Stack-based function calls
17		−	- Stack is software-managed and grows downward
	15	+	- Editor with undo/redo, breakpoint and error markers in the gutter —
	16	+	or press Ctrl-G to edit in your own `$EDITOR` (vim, nvim, nano, …).
	17	+	- Two-pass assembler for the full 8051 instruction set (all 255 opcodes):
	18	+	- labels, expressions (`+ - * / MOD AND OR XOR NOT SHL SHR HIGH LOW`, `$`)
	19	+	- number formats `42`, `2Ah`, `0x2A`, `101010b`, `52o`, `'*'`
	20	+	- bit addressing (`P1.3`, `ACC.7`, `20h.0`) and all predefined SFR/bit names
	21	+	- directives `ORG DB DW DS END EQU SET BIT DATA IDATA XDATA CODE CSEG AT`
	22	+	- generic `JMP`/`CALL` (assembled as `LJMP`/`LCALL`)
	23	+	- Keil-style `.lst` listing with symbol table, Intel HEX output
	24	+	- Simulator
	25	+	- all instructions with correct flags (CY, AC, OV, P) and machine-cycle counts
	26	+	- 4 register banks, 256 bytes IRAM, SFRs, 64K code, 64K XRAM
	27	+	- ports P0–P3 with latch vs. pin semantics (read-modify-write reads the latch)
	28	+	- timers 0/1 in modes 0–3, gate and counter inputs
	29	+	- interrupts: INT0, T0, INT1, T1, serial; two priority levels; edge/level triggers
	30	+	- UART in modes 0–3 with baud rate timing from timer 1
	31	+	- idle and power-down modes (PCON)
	32	+	- Debugger: run / pause, step into / over / out, run to cursor,
	33	+	breakpoints, changed-value highlighting, memory poke, adjustable speed.
	34	+	- Open `.hex` files: they're disassembled into editable source that
	35	+	re-assembles to the identical image.
18	36
19		−	---
20		−
21		−
22		−
23		−	## Registers
24		−	\| Register \| Size \| Description \|
25		−	\| -------- \| ------ \| ------------------------------ \|
26		−	\| A \| 8-bit \| General-purpose register \|
27		−	\| B \| 8-bit \| General-purpose register \|
28		−	\| C \| 8-bit \| General-purpose register \|
29		−	\| D \| 8-bit \| General-purpose register \|
30		−	\| PC \| 16-bit \| Program Counter \|
31		−	\| SP \| 16-bit \| Stack pointer \|
32		−
33		−
34		−	## Flags Register
35		−
36		−	The CPU maintains a small flags register.
37		−
38		−	\| Flag \| Description \|
39		−	\| ----- \| ------------ \|
40		−	\| Z \| Zero flag - set if last result was `0` \|
41		−	\| C \| Carry/Borrow flag \|
42		−
43		−	- Control-flow instructions do not modify flags.
44		−
45		−	## Supported Instructions
46		−
47		−	\| Instruction \| Syntax \|
48		−	\| ----------- \| ---------------- \|
49		−	\| MOV \| mov dest, src OR mov reg, imm \|
50		−	\| ADD \| add r1, r2 OR add reg, imm \|
51		−	\| SUB \| sub r1, r2 OR sub reg, imm \|
52		−	\| JMP \| jmp addr OR jmp addr \|
53		−	\| JZ \| jz addr OR jz addr \|
54		−	\| JNZ \| jnz addr OR jnz addr \|
55		−	\| CMP \| cmp r1, r2 OR cmp reg, imp \|
56		−	\| MUL \| mul r1, r2 \|
57		−	\| DIV \| div r1, r2 \|
58		−	\| CALL \| call \<label\> \|
59		−	\| SYS \| sys \<syscall_no\> \|
60		−	\| HLT (Halt) \| hlt \|
61		−
62		−	## Syscalls
63		−
64		−	\| Imm \| Meaning \|
65		−	\| --- \| ------- \|
66		−	\| 0 \| Exit Program \|
67		−	\| 1 \| Print register A as integer \|
68		−	\| 2 \| Print register A as ASCII char \|
69		−
70		−	- Syscalls also do not modify flags
71		−
72		−	## Example assembly program
73		−
74		−	```assembly
75		−	mov b, 3
76		−	mov a, 1
	37	+	## Usage
77	38
78		−	loop:
79		−	sub b, a
80		−	jnz loop
	39	+	```bash
	40	+	cargo run --release -- examples/serial_hello.asm # open in the TUI
	41	+	cargo run --release # start with a template
	42	+	cargo run --release -- firmware.hex # disassemble & debug a HEX file
81	43
82		−	sys 1 ; print register A
83		−	sys 0 ; exit
	44	+	# Headless assembly: writes prog.hex and prog.lst
	45	+	cargo run --release -- --assemble prog.asm
	46	+	cargo run --release -- --assemble prog.asm -o out.hex --lst out.lst
84	47		```
85	48
86		−	## Usage
	49	+	`--clock <MHz>` sets the oscillator frequency used for the elapsed-time display
	50	+	(default 11.0592).
	51	+
	52	+	## Keys
	53	+
	54	+	\| Key \| Action \|
	55	+	\| --- \| --- \|
	56	+	\| F1 \| help \|
	57	+	\| F2 / Ctrl-S \| save (assembling a saved file also writes `.lst` and `.hex` next to it) \|
	58	+	\| F3 / Ctrl-O \| open `.asm` or `.hex` \|
	59	+	\| Ctrl-G \| edit in `$EDITOR`; on save & exit the buffer reloads and reassembles \|
	60	+	\| F4 \| switch Edit ⇄ Debug \|
	61	+	\| F7 \| assemble, reset and load \|
	62	+	\| F5 \| run / pause (assembles first if the source changed) \|
	63	+	\| F11 / F10 / F12 \| step into / step over / step out \|
	64	+	\| F8 \| run to cursor \|
	65	+	\| F9 \| toggle breakpoint on the cursor line \|
	66	+	\| F6 \| reset \|
	67	+	\| Ctrl-Q \| quit \|
	68	+
	69	+	Edit mode: `Alt-1/2/3` switch between Listing, HEX and Errors; `Alt-↑/↓`,
	70	+	`Alt-PgUp/PgDn` scroll them. The editor uses Emacs-style keys
	71	+	(`Ctrl-U` undo, `Ctrl-R` redo, `Ctrl-Y` paste).
	72	+
	73	+	Debug mode: `Tab` cycles focus between Source, Memory, Ports and Serial.
	74	+	Letter shortcuts work too, for terminals that swallow function keys:
	75	+	`r` run/pause, `s` step, `n` step over, `o` step out, `g` run to cursor,
	76	+	`b` breakpoint, `x` reset, `i`/`f`/`d`/`c` show IRAM/SFR/XRAM/CODE,
	77	+	`p` poke memory, `+`/`-` speed, `.` jump to PC, `Esc` pause / back to editor.
	78	+
	79	+	- Ports: select a pin and press Space to pull it low from outside (a
	80	+	button press); the program sees the pin as `latch AND external level`.
	81	+	- Serial: type a line and press Enter to send it (followed by CR) to the
	82	+	8051's receiver; everything the 8051 transmits appears above.
	83	+
	84	+	## Examples
	85	+
	86	+	\| File \| Shows \|
	87	+	\| --- \| --- \|
	88	+	\| `examples/blink.asm` \| port toggling, delay loops, `ACALL`/`RET` \|
	89	+	\| `examples/timer_irq.asm` \| timer 0 mode 1 interrupt \|
	90	+	\| `examples/serial_hello.asm` \| UART setup, string output with `MOVC`, echo \|
	91	+	\| `examples/button_int0.asm` \| edge-triggered INT0, idle mode \|
	92	+	\| `examples/bcd_add.asm` \| `ADDC` and `DA A` with packed BCD \|
	93	+	\| `examples/lookup_movc.asm` \| 7-segment table lookup \|
	94	+
	95	+	## Notes and limitations
	96	+
	97	+	- Indirect addressing reaches all 256 bytes of IRAM (8052-style upper 128).
	98	+	- Serial input has no 9th data bit; in modes 2/3 `RB8` reads 0.
	99	+	- No 8052 timer 2, external code memory or on-chip peripherals of derivatives.
	100	+
	101	+	## Development
87	102
88	103		```bash
89		−	cargo run -- --f <examples/filename.asc>
	104	+	cargo test # assembler, CPU, peripheral and example-program tests
	105	+	cargo clippy
90	106		```
91	107
92		−	## Non-goals
93		−
94		−	1. No pipelining
95		−	2. No interrupts
96		−	3. No virtual memory
97		−	4. No privilege levels
98		−	5. No hardware I/O
99		−
100		−	## Goals
101		−
102		−	- [x] Assembler
103		−	- [x] Lexer/Tokenizer
104		−	- [x] Add label support (supporting JMP/JZ/JNZ)
105		−	- [x] Add instructions
106		−	- [x] CMP
107		−	- [x] MUL
108		−	- [x] DIV
109		−	- [x] CALL
110		−	- [x] RET
111		−	- [x] SYS
112		−	- [ ] Better error-handling
113		−	- [ ] TUI debugger
	108	+	Code layout: `src/isa.rs` (opcode table shared by everything), `src/asm/`
	109	+	(assembler, listing, Intel HEX), `src/sim/` (CPU, peripherals, disassembler),
	110	+	`src/ui/` (ratatui front end).

	@@ -0,0 +1,20 @@
1	+	; External interrupt 0 (falling edge on P3.2) counts button presses into P1.
2	+	; In debug mode, Tab to the Ports panel, select P3 bit 2 and press Space
3	+	; twice (press + release) to generate one falling edge.
4	+
5	+	ORG 0000h
6	+	LJMP main
7	+
8	+	ORG 0003h ; INT0 vector
9	+	INC P1
10	+	RETI
11	+
12	+	ORG 0030h
13	+	main: MOV P1,#00h
14	+	SETB IT0 ; edge-triggered
15	+	SETB EX0
16	+	SETB EA
17	+	sleep: ORL PCON,#01h ; idle until an interrupt arrives
18	+	SJMP sleep ; ...and go back to idle afterwards
19	+
20	+	END

	@@ -1,7 +0,0 @@
1	−	mov a, 2
2	−	call square
3	−	hlt
4	−
5	−	square:
6	−	mul a, a
7	−	ret

	@@ -1,4 +0,0 @@
1	−	mov a, 10
2	−	mov b, 10
3	−	cmp a, b
4	−	hlt

	@@ -0,0 +1,20 @@
1	+	; Count 0..9 on a common-cathode 7-segment display connected to P2,
2	+	; using a MOVC lookup table. The digit is also kept in R2.
3	+
4	+	ORG 0000h
5	+	LJMP main
6	+
7	+	ORG 0030h
8	+	main: MOV DPTR,#segs
9	+	again: MOV R2,#0
10	+	next: MOV A,R2
11	+	MOVC A,@A+DPTR ; table lookup
12	+	MOV P2,A
13	+	INC R2
14	+	CJNE R2,#10,next
15	+	SJMP again
16	+
17	+	; 0 1 2 3 4 5 6 7 8 9
18	+	segs: DB 3Fh, 06h, 5Bh, 4Fh, 66h, 6Dh, 7Dh, 07h, 7Fh, 6Fh
19	+
20	+	END

	@@ -1,13 +0,0 @@
1	−	; move imm 3 to register b
2	−	mov b, 3
3	−	; move imm 1 to register a
4	−	mov a, 1
5	−
6	−	; delcare a label
7	−	loop:
8	−	; subtract a from b
9	−	sub b, a
10	−	; jump to label "loop" until the zero flag is not set
11	−	jnz loop
12	−
13	−	hlt

	@@ -1,4 +0,0 @@
1	−	mov a, 99
2	−	mov b, 99
3	−	mul a, b
4	−	hlt

	@@ -0,0 +1,43 @@
1	+	; UART: 9600 baud at 11.0592 MHz (timer 1, mode 2, TH1 = FDh).
2	+	; Prints a greeting, then echoes everything typed in the Serial panel
3	+	; (Tab to the Serial panel in debug mode, type, press Enter).
4	+
5	+	ORG 0000h
6	+	LJMP main
7	+
8	+	ORG 0030h
9	+	main: MOV TMOD,#20h ; timer 1: mode 2 (8-bit auto-reload)
10	+	MOV TH1,#0FDh
11	+	SETB TR1
12	+	MOV SCON,#50h ; serial mode 1, receiver enabled
13	+	MOV DPTR,#msg
14	+	ACALL puts
15	+	echo: ACALL getc
16	+	ACALL putc
17	+	CJNE A,#0Dh,echo ; after CR, also send LF
18	+	MOV A,#0Ah
19	+	ACALL putc
20	+	SJMP echo
21	+
22	+	; Send the zero-terminated string at DPTR.
23	+	puts: CLR A
24	+	MOVC A,@A+DPTR
25	+	JZ done
26	+	ACALL putc
27	+	INC DPTR
28	+	SJMP puts
29	+	done: RET
30	+
31	+	putc: MOV SBUF,A
32	+	wait: JNB TI,wait
33	+	CLR TI
34	+	RET
35	+
36	+	getc: JNB RI,getc
37	+	MOV A,SBUF
38	+	CLR RI
39	+	RET
40	+
41	+	msg: DB "Hello from the 8051!", 0Dh, 0Ah, "Type something: ", 0
42	+
43	+	END

	@@ -1,7 +0,0 @@
1	−	mov a, 72 ; 'H'
2	−	sys 2
3	−	mov a, 105 ; 'i'
4	−	sys 2
5	−	mov a, 10 ; '\n'
6	−	sys 2
7	−	sys 0

	@@ -1,9 +0,0 @@
1	−	; Table of 3
2	−	mov b, 3
3	−	mov c, 10 ; Counter
4	−
5	−	loop:
6	−	add a, b
7	−	sub c, 1
8	−	jnz loop
9	−	hlt

		@@ -2,6 +2,21 @@
2	2		# It is not intended for manual editing.
3	3		version = 4
4	4
	5	+	[[package]]
	6	+	name = "aho-corasick"
	7	+	version = "1.1.5"
	8	+	source = "registry+https://github.com/rust-lang/crates.io-index"
	9	+	checksum = "c982642fa9e8606056828ee9a8505737230110bb1099153c79efe865c59d12ba"
	10	+	dependencies = [
	11	+	"memchr",
	12	+	]
	13	+
	14	+	[[package]]
	15	+	name = "allocator-api2"
	16	+	version = "0.2.21"
	17	+	source = "registry+https://github.com/rust-lang/crates.io-index"
	18	+	checksum = "683d7910e743518b0e34f1186f92494becacb047c7b6bf616c96772180fef923"
	19	+
5	20		[[package]]
6	21		name = "anstream"
7	22		version = "0.6.21"
		@@ -52,6 +67,127 @@ dependencies = [
52	67		"windows-sys",
53	68		]
54	69
	70	+	[[package]]
	71	+	name = "anyhow"
	72	+	version = "1.0.104"
	73	+	source = "registry+https://github.com/rust-lang/crates.io-index"
	74	+	checksum = "330a5ed07fa54e4702c9d6c4174f74427fc0ef6e214bbd677ae50a5099946470"
	75	+
	76	+	[[package]]
	77	+	name = "approx"
	78	+	version = "0.5.1"
	79	+	source = "registry+https://github.com/rust-lang/crates.io-index"
	80	+	checksum = "cab112f0a86d568ea0e627cc1d6be74a1e9cd55214684db5561995f6dad897c6"
	81	+	dependencies = [
	82	+	"num-traits",
	83	+	]

	@@ -0,0 +1,251 @@
1	+	use super::lexer::{Tok, Token};
2	+
3	+	#[derive(Debug, Clone)]
4	+	pub enum Expr {
5	+	Num(i64),
6	+	Sym(String, usize),
7	+	/// `$`, the current location counter.
8	+	Here,
9	+	Neg(Box<Expr>),
10	+	Not(Box<Expr>),
11	+	High(Box<Expr>),
12	+	Low(Box<Expr>),
13	+	Bin(BinOp, Box<Expr>, Box<Expr>),
14	+	}
15	+
16	+	#[derive(Debug, Clone, Copy)]
17	+	pub enum BinOp {
18	+	Add,
19	+	Sub,
20	+	Mul,
21	+	Div,
22	+	Mod,
23	+	And,
24	+	Or,
25	+	Xor,
26	+	Shl,
27	+	Shr,
28	+	/// `byte.bit` bit addressing, e.g. `P1.3` or `20h.0`.
29	+	Dot,
30	+	}
31	+
32	+	pub enum EvalError {
33	+	Undefined(String, usize),
34	+	Other(String),
35	+	}
36	+
37	+	pub trait Env {
38	+	fn lookup(&self, name: &str) -> Option<i64>;
39	+	fn here(&self) -> i64;

	@@ -0,0 +1,117 @@
1	+	//! Intel HEX reading and writing.
2	+
3	+	use std::collections::BTreeMap;
4	+	use std::fmt::Write;
5	+
6	+	const RECORD_LEN: usize = 16;
7	+
8	+	/// Writes data records for contiguous runs of bytes, then the EOF record.
9	+	pub fn write(bytes: impl Iterator<Item = (u16, u8)>) -> String {
10	+	let image: BTreeMap<u16, u8> = bytes.collect();
11	+	let mut out = String::new();
12	+	let mut run: Vec<u8> = Vec::new();
13	+	let mut run_start = 0u16;
14	+	let mut flush = \|start: u16, data: &mut Vec<u8>\| {
15	+	for (i, chunk) in data.chunks(RECORD_LEN).enumerate() {
16	+	record(
17	+	&mut out,
18	+	start.wrapping_add((i * RECORD_LEN) as u16),
19	+	0x00,
20	+	chunk,
21	+	);
22	+	}
23	+	data.clear();
24	+	};
25	+	for (&addr, &b) in &image {
26	+	if !run.is_empty() && run_start.wrapping_add(run.len() as u16) != addr {
27	+	flush(run_start, &mut run);
28	+	}
29	+	if run.is_empty() {
30	+	run_start = addr;
31	+	}
32	+	run.push(b);
33	+	}
34	+	flush(run_start, &mut run);
35	+	record(&mut out, 0, 0x01, &[]);
36	+	out
37	+	}
38	+
39	+	fn record(out: &mut String, addr: u16, kind: u8, data: &[u8]) {

	@@ -0,0 +1,175 @@
1	+	#[derive(Debug, Clone, PartialEq)]
2	+	pub enum Tok {
3	+	Ident(String),
4	+	Num(i64),
5	+	Str(Vec<u8>),
6	+	Punct(char),
7	+	/// `<<` and `>>`
8	+	Shl,
9	+	Shr,
10	+	}
11	+
12	+	#[derive(Debug, Clone)]
13	+	pub struct Token {
14	+	pub tok: Tok,
15	+	pub col: usize,
16	+	}
17	+
18	+	impl Token {
19	+	pub fn ident(&self) -> Option<&str> {
20	+	match &self.tok {
21	+	Tok::Ident(s) => Some(s),
22	+	_ => None,
23	+	}
24	+	}
25	+
26	+	pub fn is_punct(&self, c: char) -> bool {
27	+	self.tok == Tok::Punct(c)
28	+	}
29	+	}
30	+
31	+	/// Splits one source line into tokens, stopping at a `;` comment.
32	+	/// Identifiers are upper-cased (the assembler is case-insensitive).
33	+	pub fn lex(line: &str) -> Result<Vec<Token>, (usize, String)> {
34	+	let chars: Vec<char> = line.chars().collect();
35	+	let mut out = Vec::new();
36	+	let mut i = 0;
37	+	while i < chars.len() {
38	+	let c = chars[i];
39	+	let col = i;

	@@ -0,0 +1,28 @@
1	+	; Timer 0 interrupt: mode 1 (16-bit) overflow every 1000 cycles toggles P1.0
2	+	; and counts ticks in R7. The main loop just idles.
3	+
4	+	RELOAD EQU 65536 - 1000
5	+
6	+	ORG 0000h
7	+	LJMP main
8	+
9	+	ORG 000Bh ; timer 0 overflow vector
10	+	LJMP t0_isr
11	+
12	+	ORG 0030h
13	+	main: MOV SP,#5Fh
14	+	MOV TMOD,#01h ; T0: mode 1, timer
15	+	MOV TH0,#HIGH RELOAD
16	+	MOV TL0,#LOW RELOAD
17	+	SETB ET0 ; enable timer 0 interrupt
18	+	SETB EA ; global interrupt enable
19	+	SETB TR0 ; start timer 0
20	+	idle: SJMP idle
21	+
22	+	t0_isr: MOV TH0,#HIGH RELOAD
23	+	MOV TL0,#LOW RELOAD
24	+	CPL P1.0
25	+	INC R7
26	+	RETI
27	+
28	+	END

	@@ -0,0 +1,53 @@
1	+	use std::fmt::Write;
2	+
3	+	use super::AsmOutput;
4	+
5	+	const BYTES_PER_ROW: usize = 4;
6	+
7	+	/// Keil A51-style listing: location, object bytes, line number, source,
8	+	/// with errors inline and a symbol table at the end.
9	+	pub fn render(out: &AsmOutput, source: &str) -> String {
10	+	let mut s = String::new();
11	+	let _ = writeln!(s, "LOC OBJ LINE SOURCE");
12	+	let _ = writeln!(s);
13	+	let mut diags = out.diagnostics.iter().peekable();
14	+	for (i, text) in source.lines().enumerate() {
15	+	let line = out.lines.get(i).cloned().unwrap_or_default();
16	+	let loc = line.addr.map_or(" ".to_string(), \|a\| format!("{a:04X}"));
17	+	let mut chunks = line.bytes.chunks(BYTES_PER_ROW);
18	+	let obj = chunks.next().map(hex_bytes).unwrap_or_default();
19	+	let _ = writeln!(s, "{loc} {obj:<12} {:>5} {}", i + 1, text.trim_end());
20	+	let mut addr = line.addr.unwrap_or(0) as usize;
21	+	for c in chunks {
22	+	addr += BYTES_PER_ROW;
23	+	let _ = writeln!(s, "{:04X} {}", addr & 0xFFFF, hex_bytes(c));
24	+	}
25	+	while let Some(d) = diags.next_if(\|d\| d.line == i) {
26	+	let _ = writeln!(s, "*** ERROR at column {}: {}", d.col + 1, d.msg);
27	+	}
28	+	}
29	+
30	+	let _ = writeln!(s);
31	+	let _ = writeln!(s, "SYMBOL TABLE");
32	+	let _ = writeln!(s, "NAME TYPE VALUE");
33	+	for (name, sym) in &out.symbols {
34	+	let _ = writeln!(
35	+	s,
36	+	"{name:<19} {:<7} {:04X}h",
37	+	sym.kind.name(),
38	+	sym.value & 0xFFFF
39	+	);
40	+	}
41	+	let _ = writeln!(s);
42	+	let _ = writeln!(
43	+	s,
44	+	"ASSEMBLY COMPLETE: {} ERROR(S), {} BYTE(S) OF CODE",
45	+	out.diagnostics.len(),
46	+	out.code_size()
47	+	);
48	+	s
49	+	}
50	+
51	+	fn hex_bytes(b: &[u8]) -> String {
52	+	b.iter().map(\|x\| format!("{x:02X}")).collect()
53	+	}

	@@ -1,201 +0,0 @@
1	−	use crate::instructions::Instruction;
2	−	use std::collections::HashMap;
3	−
4	−	fn tokenize(line: &str) -> Vec<String> {
5	−	line.split([' ', ',', '\t'])
6	−	.filter(\|s\| !s.is_empty())
7	−	.map(\|s\| s.to_lowercase())
8	−	.collect()
9	−	}
10	−
11	−	// Returns corrensponding u8 value of the register
12	−	fn parse_reg(s: &str) -> u8 {
13	−	match s {
14	−	"a" => 0,
15	−	"b" => 1,
16	−	"c" => 2,
17	−	"d" => 3,
18	−	_ => panic!("Unknown register {}", s),
19	−	}
20	−	}
21	−
22	−	fn is_reg(s: &str) -> bool {
23	−	matches!(s, "a" \| "b" \| "c" \| "d")
24	−	}
25	−
26	−	fn instr_size(tokens: &[String]) -> u16 {
27	−	match tokens[0].as_str() {
28	−	"mov" \| "add" \| "sub" \| "jmp" \| "jz" \| "jnz" \| "cmp" \| "mul" \| "div" \| "call" => 3,
29	−	"sys" => 2,
30	−	"hlt" \| "ret" => 1,
31	−	_ => panic!("Unknown instruction {}", tokens[0]),
32	−	}
33	−	}
34	−
35	−	fn first_pass(source: &str) -> HashMap<String, u16> {
36	−	let mut symbols = HashMap::new();
37	−	let mut addr: u16 = 0;
38	−
39	−	for line in source.lines() {
40	−	let line = line.trim();
41	−
42	−	// Ignoring comments and empty lines
43	−	if line.is_empty() \|\| line.starts_with(";") {
44	−	continue;
45	−	}
46	−
47	−	// Labels (ends with ":")
48	−	if line.ends_with(":") {
49	−	let label = line.trim_end_matches(":").to_string();
50	−	symbols.insert(label, addr);
51	−	continue;
52	−	}
53	−
54	−	let tokens = tokenize(line);
55	−	addr += instr_size(&tokens);
56	−	}
57	−
58	−	symbols
59	−	}
60	−
61	−	pub fn assembler(source: &str) -> Vec<u8> {
62	−	let symbols = first_pass(source);
63	−	let mut bytes = Vec::new();
64	−
65	−	for (line_no, line) in source.lines().enumerate() {
66	−	let line = line.trim();
67	−
68	−	// Comments in assembly start with ";"
69	−	if line.is_empty() \|\| line.starts_with(';') \|\| line.ends_with(":") {
70	−	continue;
71	−	}
72	−
73	−	let tokens = tokenize(line);
74	−
75	−	match tokens[0].as_str() {
76	−	"mov" => {
77	−	// mov reg, imm
78	−	let r1 = parse_reg(&tokens[1]);
79	−	if is_reg(&tokens[2]) {
80	−	let r2 = parse_reg(&tokens[2]);
81	−	bytes.push(Instruction::MOV_RR as u8);
82	−	bytes.push(r1);
83	−	bytes.push(r2);
84	−	} else {
85	−	let imm: u8 = tokens[2].parse().unwrap();
86	−	bytes.push(Instruction::MOV_RI as u8);
87	−	bytes.push(r1);
88	−	bytes.push(imm);
89	−	}
90	−	}
91	−
92	−	"add" => {
93	−	// add a, b
94	−	let r1 = parse_reg(&tokens[1]);
95	−
96	−	if is_reg(&tokens[2]) {
97	−	let r2 = parse_reg(&tokens[2]);
98	−	bytes.push(Instruction::ADD_RR as u8);
99	−	bytes.push(r1);
100	−	bytes.push(r2);
101	−	} else {
102	−	let imm: u8 = tokens[2].parse().unwrap();
103	−	bytes.push(Instruction::ADD_RI as u8);
104	−	bytes.push(r1);
105	−	bytes.push(imm);
106	−	}
107	−	}
108	−
109	−	"sub" => {
110	−	// sub a, b
111	−	let r1 = parse_reg(&tokens[1]);
112	−	if is_reg(&tokens[2]) {
113	−	let r2 = parse_reg(&tokens[2]);
114	−	bytes.push(Instruction::SUB_RR as u8);
115	−	bytes.push(r1);
116	−	bytes.push(r2);
117	−	} else {
118	−	let imm: u8 = tokens[2].parse().unwrap();
119	−	bytes.push(Instruction::SUB_RI as u8);
120	−	bytes.push(r1);
121	−	bytes.push(imm);
122	−	}
123	−	}
124	−
125	−	"jmp" \| "jz" \| "jnz" => {
126	−	let opcode = match tokens[0].as_str() {
127	−	"jmp" => Instruction::JMP,
128	−	"jz" => Instruction::JZ,
129	−	"jnz" => Instruction::JNZ,
130	−	_ => unreachable!(),
131	−	};
132	−
133	−	let label = &tokens[1];
134	−	let addr = *symbols.get(label).expect("Uknown label");
135	−
136	−	bytes.push(opcode as u8);
137	−	bytes.push((addr & 0xFF) as u8); // low
138	−	bytes.push((addr >> 8) as u8); // high
139	−	}
140	−
141	−	"cmp" => {
142	−	let r1 = parse_reg(&tokens[1]);
143	−	if tokens[2].chars().all(\|c\| c.is_ascii_digit()) {
144	−	let imm: u8 = tokens[2].parse().unwrap();
145	−	bytes.push(Instruction::CMP_RI as u8);
146	−	bytes.push(r1);
147	−	bytes.push(imm);
148	−	} else {
149	−	let r2 = parse_reg(&tokens[2]);
150	−	bytes.push(Instruction::CMP_RR as u8);
151	−	bytes.push(r1);
152	−	bytes.push(r2);
153	−	}
154	−	}
155	−
156	−	"mul" => {
157	−	let r1 = parse_reg(&tokens[1]);
158	−	let r2 = parse_reg(&tokens[2]);
159	−
160	−	bytes.push(Instruction::MUL as u8);
161	−	bytes.push(r1);
162	−	bytes.push(r2);
163	−	}
164	−
165	−	"div" => {
166	−	let r1 = parse_reg(&tokens[1]);
167	−	let r2 = parse_reg(&tokens[2]);
168	−
169	−	bytes.push(Instruction::DIV as u8);
170	−	bytes.push(r1);
171	−	bytes.push(r2);
172	−	}
173	−
174	−	"call" => {
175	−	let addr = *symbols.get(&tokens[1]).expect("Unknown label");
176	−
177	−	bytes.push(Instruction::CALL as u8);
178	−	bytes.push((addr & 0xFF) as u8); // low
179	−	bytes.push((addr >> 8) as u8); // high
180	−	}
181	−
182	−	"ret" => {
183	−	bytes.push(Instruction::RET as u8);
184	−	}
185	−
186	−	"hlt" => {
187	−	bytes.push(Instruction::HLT as u8);
188	−	}
189	−
190	−	"sys" => {
191	−	let imm = tokens[1].parse().unwrap();
192	−	bytes.push(Instruction::SYS as u8);
193	−	bytes.push(imm);
194	−	}
195	−
196	−	_ => panic!("Line {}: unknown instruction", line_no + 1),
197	−	}
198	−	}
199	−
200	−	bytes
201	−	}

	@@ -1,424 +0,0 @@
1	−	use crate::instructions::Instruction;
2	−	use crate::memory::Memory;
3	−
4	−	#[derive(Default, Debug)]
5	−	#[allow(dead_code)]
6	−	pub struct CPU {
7	−	pub a: u8,
8	−	pub b: u8,
9	−	pub c: u8,
10	−	pub d: u8,
11	−
12	−	pub pc: u16,
13	−	pub sp: u16,
14	−
15	−	pub zero: bool,
16	−	pub carry: bool,
17	−
18	−	pub halted: bool,
19	−	}
20	−
21	−	impl CPU {
22	−	fn push16(&mut self, mem: &mut Memory, val: u16) {
23	−	self.dec_sp();
24	−	mem.write(self.sp, (val >> 8) as u8); // high
25	−	self.dec_sp();
26	−	mem.write(self.sp, (val & 0xFF) as u8); // low
27	−	}
28	−
29	−	fn pop16(&mut self, mem: &mut Memory) -> u16 {
30	−	let low = mem.read(self.sp) as u16;
31	−	self.inc_sp();
32	−	let high = mem.read(self.sp) as u16;
33	−	self.inc_sp();
34	−
35	−	(high << 8) \| low
36	−	}
37	−
38	−	pub fn debug_instr(&self, mem: &Memory) {
39	−	let opcode = mem.read(self.pc);
40	−
41	−	println!(
42	−	"PC={:04X} {:<3} \| A={:02X} B={:02X} C={:02X} D={:02X} \| Z={} C={}",
43	−	self.pc,
44	−	Instruction::opcode_name(opcode),
45	−	self.a,
46	−	self.b,
47	−	self.c,
48	−	self.d,
49	−	self.zero as u8,
50	−	self.carry as u8
51	−	);
52	−	}
53	−
54	−	pub fn step(&mut self, mem: &mut Memory) {
55	−	let opcode = mem.read(self.pc);
56	−	self.inc_pc();
57	−
58	−	match opcode {
59	−	x if x == Instruction::MOV_RI as u8 => self.mov_ri(mem),
60	−	x if x == Instruction::MOV_RR as u8 => self.mov_rr(mem),
61	−	x if x == Instruction::ADD_RR as u8 => self.add_rr(mem),
62	−	x if x == Instruction::ADD_RI as u8 => self.add_ri(mem),
63	−	x if x == Instruction::SUB_RR as u8 => self.sub_rr(mem),
64	−	x if x == Instruction::SUB_RI as u8 => self.sub_ri(mem),
65	−	x if x == Instruction::JMP as u8 => self.jmp(mem),
66	−	x if x == Instruction::JZ as u8 => self.jz(mem),
67	−	x if x == Instruction::JNZ as u8 => self.jnz(mem),
68	−	x if x == Instruction::CMP_RI as u8 => self.cmp_ri(mem),
69	−	x if x == Instruction::CMP_RR as u8 => self.cmp_rr(mem),
70	−	x if x == Instruction::MUL as u8 => self.mul(mem),
71	−	x if x == Instruction::DIV as u8 => self.div(mem),
72	−	x if x == Instruction::CALL as u8 => self.call(mem),
73	−	x if x == Instruction::RET as u8 => self.ret(mem),
74	−	x if x == Instruction::SYS as u8 => self.syscall(mem),
75	−	x if x == Instruction::HLT as u8 => self.halt(),
76	−	_ => panic!("Unknown opcode {:02X}", opcode),
77	−	}
78	−	}
79	−
80	−	pub fn inc_pc(&mut self) {
81	−	self.pc += 1;
82	−	}
83	−
84	−	pub fn inc_sp(&mut self) {
85	−	self.sp = self.sp.wrapping_add(1);
86	−	}
87	−
88	−	pub fn dec_sp(&mut self) {
89	−	self.sp = self.sp.wrapping_sub(1);
90	−	}
91	−
92	−	pub fn halt(&mut self) {
93	−	self.halted = true;
94	−	}
95	−
96	−	pub fn mov_ri(&mut self, mem: &Memory) {
97	−	let reg = mem.read(self.pc);
98	−	self.inc_pc();
99	−	let val = mem.read(self.pc);
100	−	self.inc_pc();
101	−
102	−	match reg {
103	−	0 => self.a = val,
104	−	1 => self.b = val,
105	−	2 => self.c = val,
106	−	3 => self.d = val,
107	−	_ => {}
108	−	}
109	−
110	−	self.zero = val == 0;
111	−	}
112	−
113	−	pub fn mov_rr(&mut self, mem: &Memory) {
114	−	let dest = mem.read(self.pc);
115	−	self.inc_pc();
116	−	let src = mem.read(self.pc);
117	−	self.inc_pc();
118	−
119	−	let val = self.get_reg(src);
120	−	self.set_reg(dest, val);
121	−
122	−	self.zero = val == 0;
123	−	}
124	−
125	−	pub fn add_rr(&mut self, mem: &Memory) {
126	−	let dest = mem.read(self.pc);
127	−	self.pc += 1;
128	−	let src = mem.read(self.pc);
129	−	self.pc += 1;
130	−
131	−	let (result, carry) = match (dest, src) {
132	−	(0, 0) => self.a.overflowing_add(self.a),
133	−	(0, 1) => self.a.overflowing_add(self.b),
134	−	(0, 2) => self.a.overflowing_add(self.c),
135	−	(0, 3) => self.a.overflowing_add(self.d),
136	−
137	−	(1, 0) => self.b.overflowing_add(self.a),
138	−	(1, 1) => self.b.overflowing_add(self.b),
139	−	(1, 2) => self.b.overflowing_add(self.c),
140	−	(1, 3) => self.b.overflowing_add(self.d),
141	−
142	−	(2, 0) => self.c.overflowing_add(self.a),
143	−	(2, 1) => self.c.overflowing_add(self.b),
144	−	(2, 2) => self.c.overflowing_add(self.c),
145	−	(2, 3) => self.c.overflowing_add(self.d),
146	−
147	−	(3, 0) => self.d.overflowing_add(self.a),
148	−	(3, 1) => self.d.overflowing_add(self.b),
149	−	(3, 2) => self.d.overflowing_add(self.c),
150	−	(3, 3) => self.d.overflowing_add(self.d),
151	−
152	−	_ => (0, false),
153	−	};
154	−
155	−	match dest {
156	−	0 => self.a = result,
157	−	1 => self.b = result,
158	−	2 => self.c = result,
159	−	3 => self.d = result,
160	−	_ => {}
161	−	}
162	−
163	−	self.zero = result == 0;
164	−	self.carry = carry;
165	−	}
166	−	pub fn add_ri(&mut self, mem: &Memory) {
167	−	let dest = mem.read(self.pc);
168	−	self.pc += 1;
169	−	let imm = mem.read(self.pc);
170	−	self.pc += 1;
171	−
172	−	let (result, carry) = match dest {
173	−	0 => self.a.overflowing_add(imm),
174	−	1 => self.b.overflowing_add(imm),
175	−	2 => self.c.overflowing_add(imm),
176	−	3 => self.d.overflowing_add(imm),
177	−	_ => (0, false),
178	−	};
179	−
180	−	match dest {
181	−	0 => self.a = result,
182	−	1 => self.b = result,
183	−	2 => self.c = result,
184	−	3 => self.d = result,
185	−	_ => {}
186	−	}
187	−
188	−	self.zero = result == 0;
189	−	self.carry = carry;
190	−	}
191	−
192	−	pub fn sub_rr(&mut self, mem: &Memory) {
193	−	let dest = mem.read(self.pc);
194	−	self.pc += 1;
195	−	let src = mem.read(self.pc);
196	−	self.pc += 1;
197	−
198	−	let (result, borrow) = match (dest, src) {
199	−	(0, 0) => self.a.overflowing_sub(self.a),
200	−	(0, 1) => self.a.overflowing_sub(self.b),
201	−	(0, 2) => self.a.overflowing_sub(self.c),
202	−	(0, 3) => self.a.overflowing_sub(self.d),
203	−
204	−	(1, 0) => self.b.overflowing_sub(self.a),
205	−	(1, 1) => self.b.overflowing_sub(self.b),
206	−	(1, 2) => self.b.overflowing_sub(self.c),
207	−	(1, 3) => self.b.overflowing_sub(self.d),
208	−
209	−	(2, 0) => self.c.overflowing_sub(self.a),
210	−	(2, 1) => self.c.overflowing_sub(self.b),
211	−	(2, 2) => self.c.overflowing_sub(self.c),
212	−	(2, 3) => self.c.overflowing_sub(self.d),
213	−
214	−	(3, 0) => self.d.overflowing_sub(self.a),
215	−	(3, 1) => self.d.overflowing_sub(self.b),
216	−	(3, 2) => self.d.overflowing_sub(self.c),
217	−	(3, 3) => self.d.overflowing_sub(self.d),
218	−
219	−	_ => (0, false),
220	−	};
221	−
222	−	match dest {
223	−	0 => self.a = result,
224	−	1 => self.b = result,
225	−	2 => self.c = result,
226	−	3 => self.d = result,
227	−	_ => {}
228	−	}
229	−
230	−	self.zero = result == 0;
231	−	self.carry = borrow;
232	−	}
233	−
234	−	pub fn sub_ri(&mut self, mem: &Memory) {
235	−	let dest = mem.read(self.pc);
236	−	self.pc += 1;
237	−	let imm = mem.read(self.pc);
238	−	self.pc += 1;
239	−
240	−	let (result, borrow) = match dest {
241	−	0 => self.a.overflowing_sub(imm),
242	−	1 => self.b.overflowing_sub(imm),
243	−	2 => self.c.overflowing_sub(imm),
244	−	3 => self.d.overflowing_sub(imm),
245	−	_ => (0, false),
246	−	};
247	−
248	−	match dest {
249	−	0 => self.a = result,
250	−	1 => self.b = result,
251	−	2 => self.c = result,
252	−	3 => self.d = result,
253	−	_ => {}
254	−	}
255	−
256	−	self.zero = result == 0;
257	−	self.carry = borrow;
258	−	}
259	−
260	−	pub fn jmp(&mut self, mem: &Memory) {
261	−	let low = mem.read(self.pc) as u16;
262	−	self.inc_pc();
263	−	let high = mem.read(self.pc) as u16;
264	−	self.inc_pc();
265	−
266	−	let addrs = (high << 8) \| low;
267	−
268	−	self.pc = addrs;
269	−	}
270	−
271	−	pub fn jz(&mut self, mem: &Memory) {
272	−	let low = mem.read(self.pc) as u16;
273	−	self.inc_pc();
274	−	let high = mem.read(self.pc) as u16;
275	−	self.inc_pc();
276	−
277	−	let addrs = (high << 8) \| low;
278	−
279	−	if self.zero {
280	−	self.pc = addrs;
281	−	}
282	−	}
283	−
284	−	pub fn jnz(&mut self, mem: &Memory) {
285	−	let low = mem.read(self.pc) as u16;
286	−	self.inc_pc();
287	−	let high = mem.read(self.pc) as u16;
288	−	self.inc_pc();
289	−
290	−	let addrs = (high << 8) \| low;
291	−
292	−	if !self.zero {
293	−	self.pc = addrs;
294	−	}
295	−	}
296	−
297	−	pub fn cmp_rr(&mut self, mem: &Memory) {
298	−	let r1 = mem.read(self.pc);
299	−	self.inc_pc();
300	−	let r2 = mem.read(self.pc);
301	−	self.inc_pc();
302	−
303	−	let v1 = self.get_reg(r1);
304	−	let v2 = self.get_reg(r2);
305	−
306	−	let (result, borrow) = v1.overflowing_sub(v2);
307	−
308	−	self.zero = result == 0;
309	−	self.carry = borrow;
310	−	}
311	−
312	−	pub fn cmp_ri(&mut self, mem: &Memory) {
313	−	let r1 = mem.read(self.pc);
314	−	self.inc_pc();
315	−	let r2 = mem.read(self.pc);
316	−	self.inc_pc();
317	−
318	−	let v1 = self.get_reg(r1);
319	−
320	−	let (result, borrow) = v1.overflowing_sub(r2);
321	−
322	−	self.zero = result == 0;
323	−	self.carry = borrow;
324	−	}
325	−
326	−	pub fn mul(&mut self, mem: &Memory) {
327	−	let dest = mem.read(self.pc);
328	−	self.inc_pc();
329	−	let src = mem.read(self.pc);
330	−	self.inc_pc();
331	−
332	−	let lhs = self.get_reg(dest);
333	−	let rhs = self.get_reg(src);
334	−
335	−	let result16 = (lhs as u16) * (rhs as u16);
336	−	let result8 = (result16 & 0xFF) as u8;
337	−
338	−	self.set_reg(dest, result8);
339	−
340	−	self.zero = result8 == 0;
341	−	self.carry = result16 > 0xFF;
342	−	}
343	−
344	−	pub fn div(&mut self, mem: &Memory) {
345	−	let dest = mem.read(self.pc);
346	−	self.inc_pc();
347	−	let src = mem.read(self.pc);
348	−	self.inc_pc();
349	−
350	−	let lhs = self.get_reg(dest);
351	−	let rhs = self.get_reg(src);
352	−
353	−	if rhs == 0 {
354	−	panic!("Division by zero");
355	−	// OR: set halted = true
356	−	// OR: define a syscall/exception later
357	−	}
358	−
359	−	let result = lhs / rhs;
360	−
361	−	self.set_reg(dest, result);
362	−
363	−	self.zero = result == 0;
364	−	// carry unchanged
365	−	}
366	−
367	−	pub fn call(&mut self, mem: &mut Memory) {
368	−	let low = mem.read(self.pc) as u16;
369	−	self.inc_pc();
370	−	let high = mem.read(self.pc) as u16;
371	−	self.inc_pc();
372	−	let addr = (high << 8) \| low;
373	−
374	−	let return_addr = self.pc;
375	−
376	−	self.push16(mem, return_addr);
377	−	self.pc = addr;
378	−	}
379	−
380	−	pub fn ret(&mut self, mem: &mut Memory) {
381	−	let addr = self.pop16(mem);
382	−	self.pc = addr;
383	−	}
384	−
385	−	pub fn syscall(&mut self, mem: &Memory) {
386	−	let num = mem.read(self.pc);
387	−	self.pc = self.pc.wrapping_add(1);
388	−	match num {
389	−	0 => {
390	−	// exit
391	−	self.halted = true;
392	−	}
393	−	1 => {
394	−	// print A as number
395	−	println!("{}", self.a);
396	−	}
397	−	2 => {
398	−	// print A as ASCII char
399	−	print!("{}", self.a as char);
400	−	}
401	−	_ => panic!("Unknown syscall {}", num),
402	−	}
403	−	}
404	−
405	−	fn get_reg(&self, r: u8) -> u8 {
406	−	match r {
407	−	0 => self.a,
408	−	1 => self.b,
409	−	2 => self.c,
410	−	3 => self.d,
411	−	_ => panic!("Invalid Register"),
412	−	}
413	−	}
414	−
415	−	fn set_reg(&mut self, dest: u8, val: u8) {
416	−	match dest {
417	−	0 => self.a = val,
418	−	1 => self.b = val,
419	−	2 => self.c = val,
420	−	3 => self.d = val,
421	−	_ => panic!("Invalid register"),
422	−	}
423	−	}
424	−	}

	@@ -1,43 +0,0 @@
1	−	#[repr(u8)]
2	−	#[allow(non_camel_case_types)]
3	−	pub enum Instruction {
4	−	MOV_RI = 0x01,
5	−	MOV_RR = 0x08,
6	−	ADD_RR = 0x02,
7	−	ADD_RI = 0x0A,
8	−	SUB_RR = 0x03,
9	−	SUB_RI = 0x0B,
10	−	JMP = 0x04,
11	−	JZ = 0x05,
12	−	JNZ = 0x06,
13	−	CMP_RI = 0x07,
14	−	CMP_RR = 0x09,
15	−	MUL = 0x0C,
16	−	DIV = 0x0D,
17	−	CALL = 0x0E,
18	−	RET = 0x0F,
19	−	SYS = 0x10,
20	−	HLT = 0xFF,
21	−	}
22	−
23	−	impl Instruction {
24	−	pub fn opcode_name(op: u8) -> &'static str {
25	−	match op {
26	−	0x01 \| 0x08 => "MOV",
27	−	0x02 \| 0x0A => "ADD",
28	−	0x03 \| 0x0B => "SUB",
29	−	0x04 => "JMP",
30	−	0x05 => "JZ",
31	−	0x06 => "JNZ",
32	−	0x07 \| 0x09 => "CMP",
33	−	0x0C => "MUL",
34	−	0x0D => "DIV",
35	−	0x0E => "CALL",
36	−	0x0F => "RET",
37	−	0x10 => "SYS",
38	−	0xFF => "HLT",
39	−
40	−	_ => "???",
41	−	}
42	−	}
43	−	}

	@@ -0,0 +1,347 @@
1	+	//! The 8051 instruction set as a single opcode table, shared by the
2	+	//! assembler (pattern -> opcode), the disassembler and the simulator
3	+	//! (sizes and machine-cycle counts).
4	+
5	+	use std::sync::OnceLock;
6	+
7	+	/// Operand forms as they appear in an instruction encoding.
8	+	#[derive(Debug, Clone, Copy, PartialEq, Eq)]
9	+	pub enum Operand {
10	+	A,
11	+	AB,
12	+	C,
13	+	Dptr,
14	+	Reg(u8),
15	+	AtReg(u8),
16	+	AtDptr,
17	+	AtAPlusDptr,
18	+	AtAPlusPc,
19	+	Imm8,
20	+	Imm16,
21	+	Direct,
22	+	Bit,
23	+	NotBit,
24	+	Addr11,
25	+	Addr16,
26	+	Rel,
27	+	}
28	+
29	+	impl Operand {
30	+	/// Bytes this operand occupies after the opcode byte.
31	+	pub fn len(self) -> u8 {
32	+	match self {
33	+	Operand::Imm8 \| Operand::Direct \| Operand::Bit \| Operand::NotBit => 1,
34	+	Operand::Addr11 \| Operand::Rel => 1,
35	+	Operand::Imm16 \| Operand::Addr16 => 2,
36	+	_ => 0,
37	+	}
38	+	}
39	+	}
40	+
41	+	#[derive(Debug, Clone, Copy)]
42	+	pub struct OpInfo {
43	+	pub opcode: u8,
44	+	pub mnemonic: &'static str,
45	+	pub operands: &'static [Operand],
46	+	pub size: u8,
47	+	pub cycles: u8,
48	+	}
49	+
50	+	use Operand::*;
51	+
52	+	const RN: [[Operand; 1]; 8] = [
53	+	[Reg(0)],
54	+	[Reg(1)],
55	+	[Reg(2)],
56	+	[Reg(3)],
57	+	[Reg(4)],
58	+	[Reg(5)],
59	+	[Reg(6)],
60	+	[Reg(7)],
61	+	];
62	+	const A_RN: [[Operand; 2]; 8] = [
63	+	[A, Reg(0)],
64	+	[A, Reg(1)],
65	+	[A, Reg(2)],
66	+	[A, Reg(3)],
67	+	[A, Reg(4)],
68	+	[A, Reg(5)],
69	+	[A, Reg(6)],
70	+	[A, Reg(7)],
71	+	];
72	+	const RN_A: [[Operand; 2]; 8] = [
73	+	[Reg(0), A],
74	+	[Reg(1), A],
75	+	[Reg(2), A],
76	+	[Reg(3), A],
77	+	[Reg(4), A],
78	+	[Reg(5), A],
79	+	[Reg(6), A],
80	+	[Reg(7), A],
81	+	];
82	+	const RN_IMM: [[Operand; 2]; 8] = [
83	+	[Reg(0), Imm8],
84	+	[Reg(1), Imm8],
85	+	[Reg(2), Imm8],
86	+	[Reg(3), Imm8],
87	+	[Reg(4), Imm8],
88	+	[Reg(5), Imm8],
89	+	[Reg(6), Imm8],
90	+	[Reg(7), Imm8],
91	+	];
92	+	const DIR_RN: [[Operand; 2]; 8] = [
93	+	[Direct, Reg(0)],
94	+	[Direct, Reg(1)],
95	+	[Direct, Reg(2)],
96	+	[Direct, Reg(3)],
97	+	[Direct, Reg(4)],
98	+	[Direct, Reg(5)],
99	+	[Direct, Reg(6)],
100	+	[Direct, Reg(7)],
101	+	];
102	+	const RN_DIR: [[Operand; 2]; 8] = [
103	+	[Reg(0), Direct],
104	+	[Reg(1), Direct],
105	+	[Reg(2), Direct],
106	+	[Reg(3), Direct],
107	+	[Reg(4), Direct],
108	+	[Reg(5), Direct],
109	+	[Reg(6), Direct],
110	+	[Reg(7), Direct],
111	+	];
112	+	const RN_REL: [[Operand; 2]; 8] = [
113	+	[Reg(0), Rel],
114	+	[Reg(1), Rel],
115	+	[Reg(2), Rel],
116	+	[Reg(3), Rel],
117	+	[Reg(4), Rel],
118	+	[Reg(5), Rel],
119	+	[Reg(6), Rel],
120	+	[Reg(7), Rel],
121	+	];
122	+	const RN_IMM_REL: [[Operand; 3]; 8] = [
123	+	[Reg(0), Imm8, Rel],
124	+	[Reg(1), Imm8, Rel],
125	+	[Reg(2), Imm8, Rel],
126	+	[Reg(3), Imm8, Rel],
127	+	[Reg(4), Imm8, Rel],
128	+	[Reg(5), Imm8, Rel],
129	+	[Reg(6), Imm8, Rel],
130	+	[Reg(7), Imm8, Rel],
131	+	];
132	+	const RI: [[Operand; 1]; 2] = [[AtReg(0)], [AtReg(1)]];
133	+	const A_RI: [[Operand; 2]; 2] = [[A, AtReg(0)], [A, AtReg(1)]];
134	+	const RI_A: [[Operand; 2]; 2] = [[AtReg(0), A], [AtReg(1), A]];
135	+	const RI_IMM: [[Operand; 2]; 2] = [[AtReg(0), Imm8], [AtReg(1), Imm8]];
136	+	const DIR_RI: [[Operand; 2]; 2] = [[Direct, AtReg(0)], [Direct, AtReg(1)]];
137	+	const RI_DIR: [[Operand; 2]; 2] = [[AtReg(0), Direct], [AtReg(1), Direct]];
138	+	const RI_IMM_REL: [[Operand; 3]; 2] = [[AtReg(0), Imm8, Rel], [AtReg(1), Imm8, Rel]];
139	+
140	+	/// Fixed (non register-indexed) opcodes.
141	+	const FIXED: &[(u8, &str, &[Operand], u8)] = &[
142	+	(0x00, "NOP", &[], 1),
143	+	(0x02, "LJMP", &[Addr16], 2),
144	+	(0x03, "RR", &[A], 1),
145	+	(0x04, "INC", &[A], 1),
146	+	(0x05, "INC", &[Direct], 1),
147	+	(0x10, "JBC", &[Bit, Rel], 2),
148	+	(0x12, "LCALL", &[Addr16], 2),
149	+	(0x13, "RRC", &[A], 1),
150	+	(0x14, "DEC", &[A], 1),
151	+	(0x15, "DEC", &[Direct], 1),
152	+	(0x20, "JB", &[Bit, Rel], 2),
153	+	(0x22, "RET", &[], 2),
154	+	(0x23, "RL", &[A], 1),
155	+	(0x24, "ADD", &[A, Imm8], 1),
156	+	(0x25, "ADD", &[A, Direct], 1),
157	+	(0x30, "JNB", &[Bit, Rel], 2),
158	+	(0x32, "RETI", &[], 2),
159	+	(0x33, "RLC", &[A], 1),
160	+	(0x34, "ADDC", &[A, Imm8], 1),
161	+	(0x35, "ADDC", &[A, Direct], 1),
162	+	(0x40, "JC", &[Rel], 2),
163	+	(0x42, "ORL", &[Direct, A], 1),
164	+	(0x43, "ORL", &[Direct, Imm8], 2),
165	+	(0x44, "ORL", &[A, Imm8], 1),
166	+	(0x45, "ORL", &[A, Direct], 1),
167	+	(0x50, "JNC", &[Rel], 2),
168	+	(0x52, "ANL", &[Direct, A], 1),
169	+	(0x53, "ANL", &[Direct, Imm8], 2),
170	+	(0x54, "ANL", &[A, Imm8], 1),
171	+	(0x55, "ANL", &[A, Direct], 1),
172	+	(0x60, "JZ", &[Rel], 2),
173	+	(0x62, "XRL", &[Direct, A], 1),
174	+	(0x63, "XRL", &[Direct, Imm8], 2),
175	+	(0x64, "XRL", &[A, Imm8], 1),
176	+	(0x65, "XRL", &[A, Direct], 1),
177	+	(0x70, "JNZ", &[Rel], 2),
178	+	(0x72, "ORL", &[C, Bit], 2),
179	+	(0x73, "JMP", &[AtAPlusDptr], 2),
180	+	(0x74, "MOV", &[A, Imm8], 1),
181	+	(0x75, "MOV", &[Direct, Imm8], 2),
182	+	(0x80, "SJMP", &[Rel], 2),
183	+	(0x82, "ANL", &[C, Bit], 2),
184	+	(0x83, "MOVC", &[A, AtAPlusPc], 2),
185	+	(0x84, "DIV", &[AB], 4),
186	+	// Encoded as: opcode, src, dest (handled specially by the encoder).
187	+	(0x85, "MOV", &[Direct, Direct], 2),
188	+	(0x90, "MOV", &[Dptr, Imm16], 2),
189	+	(0x92, "MOV", &[Bit, C], 2),
190	+	(0x93, "MOVC", &[A, AtAPlusDptr], 2),
191	+	(0x94, "SUBB", &[A, Imm8], 1),
192	+	(0x95, "SUBB", &[A, Direct], 1),
193	+	(0xA0, "ORL", &[C, NotBit], 2),
194	+	(0xA2, "MOV", &[C, Bit], 1),
195	+	(0xA3, "INC", &[Dptr], 2),
196	+	(0xA4, "MUL", &[AB], 4),
197	+	(0xB0, "ANL", &[C, NotBit], 2),
198	+	(0xB2, "CPL", &[Bit], 1),
199	+	(0xB3, "CPL", &[C], 1),
200	+	(0xB4, "CJNE", &[A, Imm8, Rel], 2),
201	+	(0xB5, "CJNE", &[A, Direct, Rel], 2),
202	+	(0xC0, "PUSH", &[Direct], 2),
203	+	(0xC2, "CLR", &[Bit], 1),
204	+	(0xC3, "CLR", &[C], 1),
205	+	(0xC4, "SWAP", &[A], 1),
206	+	(0xC5, "XCH", &[A, Direct], 1),
207	+	(0xD0, "POP", &[Direct], 2),
208	+	(0xD2, "SETB", &[Bit], 1),
209	+	(0xD3, "SETB", &[C], 1),
210	+	(0xD4, "DA", &[A], 1),
211	+	(0xD5, "DJNZ", &[Direct, Rel], 2),
212	+	(0xE0, "MOVX", &[A, AtDptr], 2),
213	+	(0xE4, "CLR", &[A], 1),
214	+	(0xE5, "MOV", &[A, Direct], 1),
215	+	(0xF0, "MOVX", &[AtDptr, A], 2),
216	+	(0xF4, "CPL", &[A], 1),
217	+	(0xF5, "MOV", &[Direct, A], 1),
218	+	];
219	+
220	+	/// Register-indexed groups: (base opcode, mnemonic, cycles, @Ri forms, Rn forms).
221	+	type Group = (
222	+	u8,
223	+	&'static str,
224	+	u8,
225	+	Option<&'static [[Operand; 2]; 2]>,
226	+	Option<&'static [[Operand; 2]; 8]>,
227	+	);
228	+	const GROUPS2: &[Group] = &[
229	+	(0x20, "ADD", 1, Some(&A_RI), Some(&A_RN)),
230	+	(0x30, "ADDC", 1, Some(&A_RI), Some(&A_RN)),
231	+	(0x40, "ORL", 1, Some(&A_RI), Some(&A_RN)),
232	+	(0x50, "ANL", 1, Some(&A_RI), Some(&A_RN)),
233	+	(0x60, "XRL", 1, Some(&A_RI), Some(&A_RN)),
234	+	(0x70, "MOV", 1, Some(&RI_IMM), Some(&RN_IMM)),
235	+	(0x80, "MOV", 2, Some(&DIR_RI), Some(&DIR_RN)),
236	+	(0x90, "SUBB", 1, Some(&A_RI), Some(&A_RN)),
237	+	(0xA0, "MOV", 2, Some(&RI_DIR), Some(&RN_DIR)),
238	+	(0xC0, "XCH", 1, Some(&A_RI), Some(&A_RN)),
239	+	(0xD0, "XCHD", 1, Some(&A_RI), None),
240	+	(0xD0, "DJNZ", 2, None, Some(&RN_REL)),
241	+	(0xE0, "MOV", 1, Some(&A_RI), Some(&A_RN)),
242	+	(0xF0, "MOV", 1, Some(&RI_A), Some(&RN_A)),
243	+	];
244	+
245	+	fn size_of(ops: &[Operand]) -> u8 {
246	+	1 + ops.iter().map(\|o\| o.len()).sum::<u8>()
247	+	}
248	+
249	+	fn build() -> Vec<Option<OpInfo>> {
250	+	let mut t: Vec<Option<OpInfo>> = vec![None; 256];
251	+	let mut put = \|opcode: u8, mnemonic: &'static str, operands: &'static [Operand], cycles: u8\| {
252	+	assert!(
253	+	t[opcode as usize].is_none(),
254	+	"duplicate opcode {opcode:02X}"
255	+	);
256	+	t[opcode as usize] = Some(OpInfo {
257	+	opcode,
258	+	mnemonic,
259	+	operands,
260	+	size: size_of(operands),
261	+	cycles,
262	+	});
263	+	};
264	+
265	+	for &(op, m, ops, cyc) in FIXED {
266	+	put(op, m, ops, cyc);
267	+	}
268	+	// AJMP / ACALL: addr11 high bits live in the opcode's top three bits.
269	+	for page in 0..8u8 {
270	+	put((page << 5) \| 0x01, "AJMP", &[Addr11], 2);
271	+	put((page << 5) \| 0x11, "ACALL", &[Addr11], 2);
272	+	}
273	+	for i in 0..2 {
274	+	put(0x06 + i as u8, "INC", &RI[i], 1);
275	+	put(0x16 + i as u8, "DEC", &RI[i], 1);
276	+	put(0xB6 + i as u8, "CJNE", &RI_IMM_REL[i], 2);
277	+	put(0xE2 + i as u8, "MOVX", &A_RI[i], 2);
278	+	put(0xF2 + i as u8, "MOVX", &RI_A[i], 2);
279	+	}
280	+	for n in 0..8 {
281	+	put(0x08 + n as u8, "INC", &RN[n], 1);
282	+	put(0x18 + n as u8, "DEC", &RN[n], 1);
283	+	put(0xB8 + n as u8, "CJNE", &RN_IMM_REL[n], 2);
284	+	}
285	+	for &(base, m, cyc, ri, rn) in GROUPS2 {
286	+	if let Some(ri) = ri {
287	+	for (i, ops) in ri.iter().enumerate() {
288	+	put(base + 6 + i as u8, m, ops, cyc);
289	+	}
290	+	}
291	+	if let Some(rn) = rn {
292	+	for (n, ops) in rn.iter().enumerate() {
293	+	put(base + 8 + n as u8, m, ops, cyc);
294	+	}
295	+	}
296	+	}
297	+	t
298	+	}
299	+
300	+	fn table() -> &'static [Option<OpInfo>] {
301	+	static TABLE: OnceLock<Vec<Option<OpInfo>>> = OnceLock::new();
302	+	TABLE.get_or_init(build)
303	+	}
304	+
305	+	/// Info for an opcode; `None` only for the reserved opcode 0xA5.
306	+	pub fn info(opcode: u8) -> Option<&'static OpInfo> {
307	+	table()[opcode as usize].as_ref()
308	+	}
309	+
310	+	/// All defined opcodes with the given mnemonic (upper case).
311	+	pub fn by_mnemonic(mnemonic: &str) -> impl Iterator<Item = &'static OpInfo> + '_ {
312	+	table()
313	+	.iter()
314	+	.flatten()
315	+	.filter(move \|i\| i.mnemonic == mnemonic)
316	+	}
317	+
318	+	pub fn is_mnemonic(s: &str) -> bool {
319	+	matches!(s, "JMP" \| "CALL") \|\| table().iter().flatten().any(\|i\| i.mnemonic == s)
320	+	}
321	+
322	+	#[cfg(test)]
323	+	mod tests {
324	+	use super::*;
325	+
326	+	#[test]
327	+	fn only_a5_is_undefined() {
328	+	let undefined: Vec<_> = (0..=255u8).filter(\|&op\| info(op).is_none()).collect();
329	+	assert_eq!(undefined, vec![0xA5]);
330	+	}
331	+
332	+	#[test]
333	+	fn spot_check_sizes_and_cycles() {
334	+	let i = info(0x85).unwrap();
335	+	assert_eq!((i.mnemonic, i.size, i.cycles), ("MOV", 3, 2));
336	+	let i = info(0xB8).unwrap();
337	+	assert_eq!((i.mnemonic, i.size, i.cycles), ("CJNE", 3, 2));
338	+	let i = info(0xD6).unwrap();
339	+	assert_eq!((i.mnemonic, i.size), ("XCHD", 1));
340	+	let i = info(0xA4).unwrap();
341	+	assert_eq!((i.mnemonic, i.cycles), ("MUL", 4));
342	+	let i = info(0xF1).unwrap();
343	+	assert_eq!((i.mnemonic, i.size), ("ACALL", 2));
344	+	let i = info(0x90).unwrap();
345	+	assert_eq!((i.mnemonic, i.size), ("MOV", 3));
346	+	}
347	+	}

		@@ -1,43 +1,95 @@
1		−	mod assembler;
2		−	mod cpu;
3		−	mod instructions;
4		−	mod memory;
	1	+	mod asm;
	2	+	mod isa;
	3	+	mod sfr;
	4	+	mod sim;
	5	+	mod ui;
5	6
6		−	use std::io;
	7	+	use std::path::PathBuf;
	8	+	use std::process::ExitCode;
7	9
8		−	use crate::assembler::assembler;
9	10		use clap::Parser;
10		−	use cpu::CPU;
11		−	use memory::Memory;
12	11
	12	+	/// Intel 8051 assembler, simulator and TUI debugger.
13	13		#[derive(Parser, Debug)]
14		−	#[command(version, about, long_about = None)]
	14	+	#[command(version, about)]
15	15		struct Args {
16		−	#[arg(short, long)]
17		−	filename: String,
18		−	}
	16	+	/// Assembly source (.asm) or Intel HEX (.hex) file to open.
	17	+	file: Option<PathBuf>,
19	18
20		−	fn main() {
21		−	let args = Args::parse();
	19	+	/// Assemble FILE without starting the TUI, writing the Intel HEX file.
	20	+	#[arg(short, long, requires = "file")]
	21	+	assemble: bool,
22	22
23		−	let mut cpu = CPU {
24		−	sp: 0xFFFE,
25		−	..Default::default()
26		−	};
27		−	let mut mem = Memory::new();
	23	+	/// Output HEX path (default: FILE with a .hex extension).
	24	+	#[arg(short, long, requires = "assemble")]
	25	+	output: Option<PathBuf>,
28	26
29		−	let asm = std::fs::read_to_string(args.filename).unwrap();
30		−	let program = assembler(&asm);
	27	+	/// Also write a listing to this path (default: FILE with a .lst extension).
	28	+	#[arg(long, requires = "assemble")]
	29	+	lst: Option<PathBuf>,
31	30
32		−	for (i, byte) in program.iter().enumerate() {
33		−	mem.write(i as u16, *byte);
34		−	}
	31	+	/// Oscillator frequency in MHz, used to show elapsed time.
	32	+	#[arg(long, default_value_t = 11.0592)]
	33	+	clock: f64,
	34	+	}
35	35
36		−	while !cpu.halted {
37		−	cpu.debug_instr(&mem);
38		−	cpu.step(&mut mem);
	36	+	fn assemble_file(args: &Args) -> ExitCode {
	37	+	let path = args.file.as_ref().unwrap();
	38	+	let source = match std::fs::read_to_string(path) {
	39	+	Ok(s) => s,
	40	+	Err(e) => {
	41	+	eprintln!("error: cannot read {}: {e}", path.display());
	42	+	return ExitCode::FAILURE;
	43	+	}
	44	+	};
	45	+	let out = asm::assemble(&source);
	46	+	let lst = args
	47	+	.lst
	48	+	.clone()
	49	+	.unwrap_or_else(\|\| path.with_extension("lst"));
	50	+	if let Err(e) = std::fs::write(&lst, out.listing(&source)) {
	51	+	eprintln!("error: cannot write {}: {e}", lst.display());
	52	+	}
	53	+	if !out.ok() {
	54	+	for d in &out.diagnostics {
	55	+	eprintln!(
	56	+	"{}:{}:{}: error: {}",
	57	+	path.display(),
	58	+	d.line + 1,
	59	+	d.col + 1,
	60	+	d.msg
	61	+	);
	62	+	}
	63	+	eprintln!("{} error(s); see {}", out.diagnostics.len(), lst.display());
	64	+	return ExitCode::FAILURE;
	65	+	}
	66	+	let hex = args
	67	+	.output
	68	+	.clone()
	69	+	.unwrap_or_else(\|\| path.with_extension("hex"));
	70	+	if let Err(e) = std::fs::write(&hex, out.intel_hex()) {
	71	+	eprintln!("error: cannot write {}: {e}", hex.display());
	72	+	return ExitCode::FAILURE;
	73	+	}
	74	+	println!(
	75	+	"{} bytes -> {}, listing -> {}",
	76	+	out.code_size(),
	77	+	hex.display(),
	78	+	lst.display()
	79	+	);
	80	+	ExitCode::SUCCESS
	81	+	}
39	82
40		−	let mut buf = String::new();
41		−	io::stdin().read_line(&mut buf).unwrap();
	83	+	fn main() -> ExitCode {
	84	+	let args = Args::parse();
	85	+	if args.assemble {
	86	+	return assemble_file(&args);
	87	+	}
	88	+	match ui::run(args.file, args.clock) {
	89	+	Ok(()) => ExitCode::SUCCESS,
	90	+	Err(e) => {
	91	+	eprintln!("error: {e}");
	92	+	ExitCode::FAILURE
	93	+	}
42	94		}
43	95		}

	@@ -1,17 +0,0 @@
1	−	pub struct Memory {
2	−	pub data: [u8; 65536],
3	−	}
4	−
5	−	impl Memory {
6	−	pub fn new() -> Self {
7	−	Self { data: [0; 65536] }
8	−	}
9	−
10	−	pub fn read(&self, addr: u16) -> u8 {
11	−	self.data[addr as usize]
12	−	}
13	−
14	−	pub fn write(&mut self, addr: u16, value: u8) {
15	−	self.data[addr as usize] = value;
16	−	}
17	−	}

	@@ -0,0 +1,146 @@
1	+	//! Special function register and bit addresses of the standard 8051.
2	+
3	+	pub const P0: u8 = 0x80;
4	+	pub const SP: u8 = 0x81;
5	+	pub const DPL: u8 = 0x82;
6	+	pub const DPH: u8 = 0x83;
7	+	pub const PCON: u8 = 0x87;
8	+	pub const TCON: u8 = 0x88;
9	+	pub const TMOD: u8 = 0x89;
10	+	pub const TL0: u8 = 0x8A;
11	+	pub const TL1: u8 = 0x8B;
12	+	pub const TH0: u8 = 0x8C;
13	+	pub const TH1: u8 = 0x8D;
14	+	pub const P1: u8 = 0x90;
15	+	pub const SCON: u8 = 0x98;
16	+	pub const SBUF: u8 = 0x99;
17	+	pub const P2: u8 = 0xA0;
18	+	pub const IE: u8 = 0xA8;
19	+	pub const P3: u8 = 0xB0;
20	+	pub const IP: u8 = 0xB8;
21	+	pub const PSW: u8 = 0xD0;
22	+	pub const ACC: u8 = 0xE0;
23	+	pub const B: u8 = 0xF0;
24	+
25	+	pub const SFRS: &[(&str, u8)] = &[
26	+	("P0", P0),
27	+	("SP", SP),
28	+	("DPL", DPL),
29	+	("DPH", DPH),
30	+	("PCON", PCON),
31	+	("TCON", TCON),
32	+	("TMOD", TMOD),
33	+	("TL0", TL0),
34	+	("TL1", TL1),
35	+	("TH0", TH0),
36	+	("TH1", TH1),
37	+	("P1", P1),
38	+	("SCON", SCON),
39	+	("SBUF", SBUF),
40	+	("P2", P2),
41	+	("IE", IE),
42	+	("P3", P3),
43	+	("IP", IP),
44	+	("PSW", PSW),
45	+	("ACC", ACC),
46	+	("B", B),
47	+	];
48	+
49	+	pub const BITS: &[(&str, u8)] = &[
50	+	("IT0", 0x88),
51	+	("IE0", 0x89),
52	+	("IT1", 0x8A),
53	+	("IE1", 0x8B),
54	+	("TR0", 0x8C),
55	+	("TF0", 0x8D),
56	+	("TR1", 0x8E),
57	+	("TF1", 0x8F),
58	+	("RI", 0x98),
59	+	("TI", 0x99),
60	+	("RB8", 0x9A),
61	+	("TB8", 0x9B),
62	+	("REN", 0x9C),
63	+	("SM2", 0x9D),
64	+	("SM1", 0x9E),
65	+	("SM0", 0x9F),
66	+	("EX0", 0xA8),
67	+	("ET0", 0xA9),
68	+	("EX1", 0xAA),
69	+	("ET1", 0xAB),
70	+	("ES", 0xAC),
71	+	("EA", 0xAF),
72	+	("RXD", 0xB0),
73	+	("TXD", 0xB1),
74	+	("INT0", 0xB2),
75	+	("INT1", 0xB3),
76	+	("T0", 0xB4),
77	+	("T1", 0xB5),
78	+	("WR", 0xB6),
79	+	("RD", 0xB7),
80	+	("PX0", 0xB8),
81	+	("PT0", 0xB9),
82	+	("PX1", 0xBA),
83	+	("PT1", 0xBB),
84	+	("PS", 0xBC),
85	+	("P", 0xD0),
86	+	("OV", 0xD2),
87	+	("RS0", 0xD3),
88	+	("RS1", 0xD4),
89	+	("F0", 0xD5),
90	+	("AC", 0xD6),
91	+	("CY", 0xD7),
92	+	];
93	+
94	+	pub fn sfr_name(addr: u8) -> Option<&'static str> {
95	+	SFRS.iter().find(\|&&(_, a)\| a == addr).map(\|&(n, _)\| n)
96	+	}
97	+
98	+	pub fn bit_name(addr: u8) -> Option<&'static str> {
99	+	BITS.iter().find(\|&&(_, a)\| a == addr).map(\|&(n, _)\| n)
100	+	}
101	+
102	+	/// Byte address and bit index of a bit address.
103	+	pub fn bit_location(bit: u8) -> (u8, u8) {
104	+	if bit < 0x80 {
105	+	(0x20 + bit / 8, bit % 8)
106	+	} else {
107	+	(bit & 0xF8, bit & 7)
108	+	}
109	+	}
110	+
111	+	/// Human-readable bit operand, e.g. `TR0`, `P1.3` or `20h.5`.
112	+	pub fn format_bit(bit: u8) -> String {
113	+	if let Some(n) = bit_name(bit) {
114	+	return n.to_string();
115	+	}
116	+	let (byte, idx) = bit_location(bit);
117	+	match sfr_name(byte) {
118	+	Some(n) => format!("{n}.{idx}"),
119	+	None => format!("{}.{idx}", hex8(byte)),
120	+	}
121	+	}
122	+
123	+	/// Human-readable direct address: SFR name or hex.
124	+	pub fn format_direct(addr: u8) -> String {
125	+	match sfr_name(addr) {
126	+	Some(n) => n.to_string(),
127	+	None => hex8(addr),
128	+	}
129	+	}
130	+
131	+	/// Assembler-style hex literal, with a leading zero when needed (`0A0h`).
132	+	pub fn hex8(v: u8) -> String {
133	+	if v >= 0xA0 {
134	+	format!("0{v:02X}h")
135	+	} else {
136	+	format!("{v:02X}h")
137	+	}
138	+	}
139	+
140	+	pub fn hex16(v: u16) -> String {
141	+	if v >= 0xA000 {
142	+	format!("0{v:04X}h")
143	+	} else {
144	+	format!("{v:04X}h")
145	+	}
146	+	}

	@@ -0,0 +1,528 @@
1	+	//! Instruction execution.
2	+
3	+	use super::{AC, CY, OV, Sim};
4	+	use crate::sfr::{B, P2};
5	+
6	+	/// Operand location for the register-indexed columns (opcode low nibble 5..F).
7	+	#[derive(Clone, Copy)]
8	+	enum Loc {
9	+	Direct(u8),
10	+	Iram(u8),
11	+	}
12	+
13	+	impl Sim {
14	+	fn fetch(&mut self) -> u8 {
15	+	let b = self.code[self.pc as usize];
16	+	self.pc = self.pc.wrapping_add(1);
17	+	b
18	+	}
19	+
20	+	fn fetch16(&mut self) -> u16 {
21	+	let h = self.fetch();
22	+	let l = self.fetch();
23	+	u16::from_be_bytes([h, l])
24	+	}
25	+
26	+	fn rel_jump(&mut self, off: u8) {
27	+	self.pc = self.pc.wrapping_add(off as i8 as u16);
28	+	}
29	+
30	+	/// Decodes the operand selected by the low nibble: 5 = direct,
31	+	/// 6/7 = @R0/@R1, 8..F = R0..R7.
32	+	fn loc(&mut self, op: u8) -> Loc {
33	+	match op & 0x0F {
34	+	0x05 => Loc::Direct(self.fetch()),
35	+	0x06 \| 0x07 => Loc::Iram(self.reg(op & 1)),
36	+	n => Loc::Iram(self.reg_addr(n & 7)),
37	+	}
38	+	}
39	+
40	+	fn read_loc(&self, l: Loc, rmw: bool) -> u8 {
41	+	match l {
42	+	Loc::Direct(a) => self.read_direct(a, rmw),
43	+	Loc::Iram(a) => self.iram[a as usize],
44	+	}
45	+	}
46	+
47	+	fn write_loc(&mut self, l: Loc, v: u8) {
48	+	match l {
49	+	Loc::Direct(a) => self.write_direct(a, v),
50	+	Loc::Iram(a) => self.iram[a as usize] = v,
51	+	}
52	+	}
53	+
54	+	/// Source operand for the arithmetic/logic rows: 4 = #imm, otherwise `loc`.
55	+	fn src(&mut self, op: u8) -> u8 {
56	+	if op & 0x0F == 0x04 {
57	+	self.fetch()
58	+	} else {
59	+	let l = self.loc(op);
60	+	self.read_loc(l, false)
61	+	}
62	+	}
63	+
64	+	fn add(&mut self, v: u8, carry: bool) {
65	+	let a = self.acc();
66	+	let c = carry as u16;
67	+	let sum = a as u16 + v as u16 + c;
68	+	let r = sum as u8;
69	+	self.set_flag(CY, sum > 0xFF);
70	+	self.set_flag(AC, (a & 0x0F) as u16 + (v & 0x0F) as u16 + c > 0x0F);
71	+	self.set_flag(OV, (a ^ r) & (v ^ r) & 0x80 != 0);
72	+	self.set_acc(r);
73	+	}
74	+
75	+	fn subb(&mut self, v: u8) {
76	+	let a = self.acc();
77	+	let c = self.flag(CY) as i16;
78	+	let diff = a as i16 - v as i16 - c;
79	+	let r = diff as u8;
80	+	self.set_flag(CY, diff < 0);
81	+	self.set_flag(AC, ((a & 0x0F) as i16) < (v & 0x0F) as i16 + c);
82	+	self.set_flag(OV, (a ^ v) & (a ^ r) & 0x80 != 0);
83	+	self.set_acc(r);
84	+	}
85	+
86	+	fn cjne(&mut self, a: u8, b: u8) {
87	+	let off = self.fetch();
88	+	self.set_flag(CY, a < b);
89	+	if a != b {
90	+	self.rel_jump(off);
91	+	}
92	+	}
93	+
94	+	fn movx_addr_ri(&self, op: u8) -> u16 {
95	+	// The high address byte comes from the P2 latch.
96	+	u16::from_be_bytes([self.sfr(P2), self.reg(op & 1)])
97	+	}
98	+
99	+	pub(super) fn execute(&mut self, op: u8) {
100	+	match op {
101	+	0x00 => {}
102	+
103	+	// AJMP / ACALL addr11
104	+	_ if op & 0x1F == 0x01 \|\| op & 0x1F == 0x11 => {
105	+	let lo = self.fetch();
106	+	let target = (self.pc & 0xF800) \| ((op as u16 >> 5) << 8) \| lo as u16;
107	+	if op & 0x10 != 0 {
108	+	self.push_pc();
109	+	}
110	+	self.pc = target;
111	+	}
112	+	0x02 => self.pc = self.fetch16(),
113	+	0x12 => {
114	+	let target = self.fetch16();
115	+	self.push_pc();
116	+	self.pc = target;
117	+	}
118	+	0x22 => self.pop_pc(),
119	+	0x32 => {
120	+	self.pop_pc();
121	+	self.in_service.pop();
122	+	self.irq_hold = true;
123	+	}
124	+	0x73 => self.pc = self.dptr().wrapping_add(self.acc() as u16),
125	+	0x80 => {
126	+	let off = self.fetch();
127	+	self.rel_jump(off);
128	+	}
129	+
130	+	// Rotates
131	+	0x03 => self.set_acc(self.acc().rotate_right(1)),
132	+	0x23 => self.set_acc(self.acc().rotate_left(1)),
133	+	0x13 => {
134	+	let a = self.acc();
135	+	self.set_acc((a >> 1) \| ((self.flag(CY) as u8) << 7));
136	+	self.set_flag(CY, a & 1 != 0);
137	+	}
138	+	0x33 => {
139	+	let a = self.acc();
140	+	self.set_acc((a << 1) \| self.flag(CY) as u8);
141	+	self.set_flag(CY, a & 0x80 != 0);
142	+	}
143	+
144	+	// INC / DEC
145	+	0x04 => self.set_acc(self.acc().wrapping_add(1)),
146	+	0x14 => self.set_acc(self.acc().wrapping_sub(1)),
147	+	0x05..=0x0F \| 0x15..=0x1F => {
148	+	let l = self.loc(op);
149	+	let v = self.read_loc(l, true);
150	+	self.write_loc(
151	+	l,
152	+	if op < 0x10 {
153	+	v.wrapping_add(1)
154	+	} else {
155	+	v.wrapping_sub(1)
156	+	},
157	+	);
158	+	}
159	+	0xA3 => self.set_dptr(self.dptr().wrapping_add(1)),
160	+
161	+	// Conditional jumps on bits
162	+	0x10 \| 0x20 \| 0x30 => {
163	+	let bit = self.fetch();
164	+	let off = self.fetch();
165	+	let set = self.read_bit(bit, op == 0x10);
166	+	if op == 0x10 && set {
167	+	self.write_bit(bit, false);
168	+	}
169	+	if set == (op != 0x30) {
170	+	self.rel_jump(off);
171	+	}
172	+	}
173	+	0x40 \| 0x50 \| 0x60 \| 0x70 => {
174	+	let off = self.fetch();
175	+	let take = match op {
176	+	0x40 => self.flag(CY),
177	+	0x50 => !self.flag(CY),
178	+	0x60 => self.acc() == 0,
179	+	_ => self.acc() != 0,
180	+	};
181	+	if take {
182	+	self.rel_jump(off);
183	+	}
184	+	}
185	+
186	+	// Arithmetic
187	+	0x24..=0x2F => {
188	+	let v = self.src(op);
189	+	self.add(v, false);
190	+	}
191	+	0x34..=0x3F => {
192	+	let v = self.src(op);
193	+	self.add(v, self.flag(CY));
194	+	}
195	+	0x94..=0x9F => {
196	+	let v = self.src(op);
197	+	self.subb(v);
198	+	}
199	+	0x84 => {
200	+	let (a, b) = (self.acc(), self.b());
201	+	self.set_flag(CY, false);
202	+	// Division by zero sets OV and leaves A and B unchanged.
203	+	match a.checked_div(b) {
204	+	Some(q) => {
205	+	self.set_acc(q);
206	+	self.set_sfr(B, a % b);
207	+	self.set_flag(OV, false);
208	+	}
209	+	None => self.set_flag(OV, true),
210	+	}
211	+	}
212	+	0xA4 => {
213	+	let r = self.acc() as u16 * self.b() as u16;
214	+	self.set_acc(r as u8);
215	+	self.set_sfr(B, (r >> 8) as u8);
216	+	self.set_flag(CY, false);
217	+	self.set_flag(OV, r > 0xFF);
218	+	}
219	+	0xD4 => {
220	+	let mut a = self.acc() as u16;
221	+	if a & 0x0F > 9 \|\| self.flag(AC) {
222	+	a += 0x06;
223	+	}
224	+	if a > 0xFF {
225	+	self.set_flag(CY, true);
226	+	}
227	+	if (a >> 4) & 0x1F > 9 \|\| self.flag(CY) {
228	+	a += 0x60;
229	+	}
230	+	if a > 0xFF {
231	+	self.set_flag(CY, true);
232	+	}
233	+	self.set_acc(a as u8);
234	+	}
235	+
236	+	// Logic: ORL/ANL/XRL direct,A / direct,#imm / A,src
237	+	0x42 \| 0x43 \| 0x52 \| 0x53 \| 0x62 \| 0x63 => {
238	+	let addr = self.fetch();
239	+	let v = if op & 1 == 1 {
240	+	self.fetch()
241	+	} else {
242	+	self.acc()
243	+	};
244	+	let d = self.read_direct(addr, true);
245	+	self.write_direct(addr, logic(op, d, v));
246	+	}
247	+	0x44..=0x4F \| 0x54..=0x5F \| 0x64..=0x6F => {
248	+	let v = self.src(op);
249	+	self.set_acc(logic(op, self.acc(), v));
250	+	}
251	+	0xC4 => self.set_acc(self.acc().rotate_left(4)),
252	+	0xE4 => self.set_acc(0),
253	+	0xF4 => self.set_acc(!self.acc()),
254	+
255	+	// Boolean (carry) operations
256	+	0x72 \| 0x82 \| 0xA0 \| 0xB0 => {
257	+	let bit = self.fetch();
258	+	let v = self.read_bit(bit, false) != (op >= 0xA0);
259	+	let c = self.flag(CY);
260	+	self.set_flag(CY, if op & 0x10 == 0 { c \|\| v } else { c && v });
261	+	}
262	+	0x92 => {
263	+	let bit = self.fetch();
264	+	self.write_bit(bit, self.flag(CY));
265	+	}
266	+	0xA2 => {
267	+	let bit = self.fetch();
268	+	self.set_flag(CY, self.read_bit(bit, false));
269	+	}
270	+	0xB2 \| 0xC2 \| 0xD2 => {
271	+	let bit = self.fetch();
272	+	let v = match op {
273	+	0xB2 => !self.read_bit(bit, true),
274	+	0xC2 => false,
275	+	_ => true,
276	+	};
277	+	self.write_bit(bit, v);
278	+	}
279	+	0xB3 => self.set_flag(CY, !self.flag(CY)),
280	+	0xC3 => self.set_flag(CY, false),
281	+	0xD3 => self.set_flag(CY, true),
282	+
283	+	// Data transfer
284	+	0x74 => {
285	+	let v = self.fetch();
286	+	self.set_acc(v);
287	+	}
288	+	0x75 => {
289	+	let addr = self.fetch();
290	+	let v = self.fetch();
291	+	self.write_direct(addr, v);
292	+	}
293	+	0x76..=0x7F => {
294	+	let l = self.loc(op);
295	+	let v = self.fetch();
296	+	self.write_loc(l, v);
297	+	}
298	+	0x85 => {
299	+	let src = self.fetch();
300	+	let dst = self.fetch();
301	+	let v = self.read_direct(src, false);
302	+	self.write_direct(dst, v);
303	+	}
304	+	0x86..=0x8F => {
305	+	let l = self.loc(op);
306	+	let addr = self.fetch();
307	+	let v = self.read_loc(l, false);
308	+	self.write_direct(addr, v);
309	+	}
310	+	0xA6..=0xAF => {
311	+	let l = self.loc(op);
312	+	let addr = self.fetch();
313	+	let v = self.read_direct(addr, false);
314	+	self.write_loc(l, v);
315	+	}
316	+	0xE5..=0xEF => {
317	+	let v = self.src(op);
318	+	self.set_acc(v);
319	+	}
320	+	0xF5..=0xFF => {
321	+	let l = self.loc(op);
322	+	self.write_loc(l, self.acc());
323	+	}
324	+	0x90 => {
325	+	let v = self.fetch16();
326	+	self.set_dptr(v);
327	+	}
328	+	0x83 => self.set_acc(self.code[self.pc.wrapping_add(self.acc() as u16) as usize]),
329	+	0x93 => self.set_acc(self.code[self.dptr().wrapping_add(self.acc() as u16) as usize]),
330	+	0xE0 => self.set_acc(self.xram[self.dptr() as usize]),
331	+	0xF0 => self.xram[self.dptr() as usize] = self.acc(),
332	+	0xE2 \| 0xE3 => self.set_acc(self.xram[self.movx_addr_ri(op) as usize]),
333	+	0xF2 \| 0xF3 => self.xram[self.movx_addr_ri(op) as usize] = self.acc(),
334	+	0xC0 => {
335	+	let addr = self.fetch();
336	+	let v = self.read_direct(addr, false);
337	+	self.push(v);
338	+	}
339	+	0xD0 => {
340	+	let addr = self.fetch();
341	+	let v = self.pop();
342	+	self.write_direct(addr, v);
343	+	}
344	+	0xC5..=0xCF => {
345	+	let l = self.loc(op);
346	+	let v = self.read_loc(l, true);
347	+	self.write_loc(l, self.acc());
348	+	self.set_acc(v);
349	+	}
350	+	0xD6 \| 0xD7 => {
351	+	let addr = self.reg(op & 1) as usize;
352	+	let (a, m) = (self.acc(), self.iram[addr]);
353	+	self.set_acc((a & 0xF0) \| (m & 0x0F));
354	+	self.iram[addr] = (m & 0xF0) \| (a & 0x0F);
355	+	}
356	+
357	+	// Compare and loop
358	+	0xB4 => {
359	+	let v = self.fetch();
360	+	self.cjne(self.acc(), v);
361	+	}
362	+	0xB5 => {
363	+	let addr = self.fetch();
364	+	let v = self.read_direct(addr, false);
365	+	self.cjne(self.acc(), v);
366	+	}
367	+	0xB6..=0xBF => {
368	+	let l = self.loc(op);
369	+	let a = self.read_loc(l, false);
370	+	let v = self.fetch();
371	+	self.cjne(a, v);
372	+	}
373	+	0xD5 \| 0xD8..=0xDF => {
374	+	let l = self.loc(op);
375	+	let v = self.read_loc(l, true).wrapping_sub(1);
376	+	self.write_loc(l, v);
377	+	let off = self.fetch();
378	+	if v != 0 {
379	+	self.rel_jump(off);
380	+	}
381	+	}
382	+
383	+	// 0xA5 is reserved and rejected before `execute` is called.
384	+	_ => unreachable!("unhandled opcode {op:02X}"),
385	+	}
386	+	}
387	+	}
388	+
389	+	fn logic(op: u8, a: u8, b: u8) -> u8 {
390	+	match op & 0xF0 {
391	+	0x40 => a \| b,
392	+	0x50 => a & b,
393	+	_ => a ^ b,
394	+	}
395	+	}
396	+
397	+	#[cfg(test)]
398	+	mod tests {
399	+	use crate::asm::assemble;
400	+	use crate::sim::{AC, CY, OV, PARITY, Sim};
401	+	use std::collections::HashSet;
402	+
403	+	/// Assembles `src`, then steps until the PC reaches the `done` label.
404	+	fn run(src: &str) -> Sim {
405	+	let src = format!("{src}\ndone: SJMP done\n");
406	+	let out = assemble(&src);
407	+	assert!(out.ok(), "{:?}", out.diagnostics);
408	+	let done = out.symbols["DONE"].value as u16;
409	+	let mut s = Sim::new();
410	+	s.load_code(out.bytes());
411	+	for _ in 0..100_000 {
412	+	if s.pc == done {
413	+	return s;
414	+	}
415	+	s.step().unwrap();
416	+	}
417	+	panic!("program did not reach 'done'");
418	+	}
419	+
420	+	#[test]
421	+	fn add_flags() {
422	+	let s = run("MOV A,#0x7F\nADD A,#1");
423	+	assert_eq!(s.acc(), 0x80);
424	+	assert!(s.flag(OV) && s.flag(AC) && !s.flag(CY));
425	+	assert!(s.flag(PARITY));
426	+	let s = run("MOV A,#0xFF\nSETB C\nADDC A,#0");
427	+	assert_eq!(s.acc(), 0);
428	+	assert!(s.flag(CY) && s.flag(AC) && !s.flag(OV));
429	+	}
430	+
431	+	#[test]
432	+	fn subb_flags() {
433	+	let s = run("CLR C\nMOV A,#0x80\nSUBB A,#1");
434	+	assert_eq!(s.acc(), 0x7F);
435	+	assert!(s.flag(OV) && s.flag(AC) && !s.flag(CY));
436	+	let s = run("SETB C\nMOV A,#5\nSUBB A,#5");
437	+	assert_eq!(s.acc(), 0xFF);
438	+	assert!(s.flag(CY));
439	+	}
440	+
441	+	#[test]
442	+	fn decimal_adjust() {
443	+	let s = run("MOV A,#0x56\nADD A,#0x67\nDA A");
444	+	assert_eq!(s.acc(), 0x23);
445	+	assert!(s.flag(CY));
446	+	let s = run("MOV A,#0x19\nADD A,#0x28\nDA A");
447	+	assert_eq!(s.acc(), 0x47);
448	+	assert!(!s.flag(CY));
449	+	}
450	+
451	+	#[test]
452	+	fn mul_div() {
453	+	let s = run("MOV A,#80\nMOV B,#160\nMUL AB");
454	+	assert_eq!((s.acc(), s.b()), (0x00, 0x32));
455	+	assert!(s.flag(OV));
456	+	let s = run("MOV A,#251\nMOV B,#18\nDIV AB");
457	+	assert_eq!((s.acc(), s.b()), (13, 17));
458	+	let s = run("MOV B,#0\nDIV AB");
459	+	assert!(s.flag(OV));
460	+	}
461	+
462	+	#[test]
463	+	fn banks_and_indirect() {
464	+	let s = run("MOV R0,#1\nSETB RS0\nMOV R0,#2\nMOV R1,#40h\nMOV @R1,#99\nMOV A,40h");
465	+	assert_eq!(s.iram[0], 1);
466	+	assert_eq!(s.iram[8], 2);
467	+	assert_eq!(s.acc(), 99);
468	+	assert_eq!(s.bank(), 1);
469	+	}
470	+
471	+	#[test]
472	+	fn stack_and_calls() {
473	+	let s = run("MOV A,#5\nPUSH ACC\nMOV A,#0\nPOP B\nCALL sub\nSJMP done\nsub: INC A\nRET");
474	+	assert_eq!(s.b(), 5);
475	+	assert_eq!(s.acc(), 1);
476	+	assert_eq!(s.sp(), 7);
477	+	}
478	+
479	+	#[test]
480	+	fn loops_and_compares() {
481	+	let s = run("MOV R2,#10\nCLR A\nl: ADD A,#2\nDJNZ R2,l");
482	+	assert_eq!(s.acc(), 20);
483	+	let s = run("MOV A,#3\nCJNE A,#5,ne\nne: NOP");
484	+	assert!(s.flag(CY));
485	+	}
486	+
487	+	#[test]
488	+	fn bits() {
489	+	let s = run("SETB 20h.3\nMOV C,20h.3\nCPL ACC.0\nANL C,/ACC.0\nMOV 21h.0,C");
490	+	assert_eq!(s.iram[0x20], 0x08);
491	+	assert_eq!(s.acc(), 1);
492	+	assert_eq!(s.iram[0x21], 0);
493	+	let s = run("SETB 20h.1\nJBC 20h.1,x\nx: NOP");
494	+	assert_eq!(s.iram[0x20], 0);
495	+	}
496	+
497	+	#[test]
498	+	fn movc_movx_xchd() {
499	+	let s = run(
500	+	"MOV DPTR,#tbl\nMOV A,#2\nMOVC A,@A+DPTR\nSJMP go\ntbl: DB 10,20,30\ngo: MOV DPTR,#1234h\nMOVX @DPTR,A\nMOV R0,#30h\nMOV @R0,#0x5A\nMOV A,#0xC3\nXCHD A,@R0",
501	+	);
502	+	assert_eq!(s.xram[0x1234], 30);
503	+	assert_eq!(s.acc(), 0xCA);
504	+	assert_eq!(s.iram[0x30], 0x53);
505	+	}
506	+
507	+	#[test]
508	+	fn ports_read_pins_but_rmw_reads_latch() {
509	+	let mut s = run("MOV P1,#0FFh");
510	+	s.pins[1] = 0xF0;
511	+	assert_eq!(s.read_direct(0x90, false), 0xF0);
512	+	assert_eq!(s.read_direct(0x90, true), 0xFF);
513	+	}
514	+
515	+	#[test]
516	+	fn step_over_and_out() {
517	+	let out = assemble("CALL f\nNOP\nSJMP $\nf: MOV A,#1\nMOV A,#2\nRET");
518	+	let mut s = Sim::new();
519	+	s.load_code(out.bytes());
520	+	let none = HashSet::new();
521	+	s.step_over(1000, &none);
522	+	assert_eq!((s.pc, s.acc()), (3, 2));
523	+	s.reset();
524	+	s.step().unwrap(); // into f
525	+	s.step_out(1000, &none);
526	+	assert_eq!(s.pc, 3);
527	+	}
528	+	}

bench51/a921fe1

rewrite as an 8051 TUI assembler, simulator and debugger

bench51a921fe1

	@@ -0,0 +1,91 @@
1	+	use crate::isa::{self, Operand};
2	+	use crate::sfr::{format_bit, format_direct, hex8, hex16};
3	+
4	+	pub struct Disasm {
5	+	pub text: String,
6	+	pub size: u8,
7	+	}
8	+
9	+	/// Disassembles the instruction at `addr`.
10	+	pub fn disassemble(code: &[u8; 0x10000], addr: u16) -> Disasm {
11	+	let byte = \|i: u16\| code[addr.wrapping_add(i) as usize];
12	+	let op = byte(0);
13	+	let Some(info) = isa::info(op) else {
14	+	return Disasm {
15	+	text: format!("DB {}", hex8(op)),
16	+	size: 1,
17	+	};
18	+	};
19	+	let next = addr.wrapping_add(info.size as u16);
20	+	let mut pos = 1u16;
21	+	let mut parts: Vec<String> = Vec::new();
22	+	for &o in info.operands {
23	+	let s = match o {
24	+	Operand::A => "A".into(),
25	+	Operand::AB => "AB".into(),
26	+	Operand::C => "C".into(),
27	+	Operand::Dptr => "DPTR".into(),
28	+	Operand::Reg(n) => format!("R{n}"),
29	+	Operand::AtReg(n) => format!("@R{n}"),
30	+	Operand::AtDptr => "@DPTR".into(),
31	+	Operand::AtAPlusDptr => "@A+DPTR".into(),
32	+	Operand::AtAPlusPc => "@A+PC".into(),
33	+	Operand::Imm8 => format!("#{}", hex8(byte(pos))),
34	+	Operand::Imm16 => format!("#{}", hex16(u16::from_be_bytes([byte(pos), byte(pos + 1)]))),
35	+	Operand::Direct => format_direct(byte(pos)),
36	+	Operand::Bit => format_bit(byte(pos)),
37	+	Operand::NotBit => format!("/{}", format_bit(byte(pos))),
38	+	Operand::Addr11 => {
39	+	hex16((next & 0xF800) \| (((op >> 5) as u16) << 8) \| byte(pos) as u16)
40	+	}
41	+	Operand::Addr16 => hex16(u16::from_be_bytes([byte(pos), byte(pos + 1)])),
42	+	Operand::Rel => hex16(next.wrapping_add(byte(pos) as i8 as u16)),
43	+	};
44	+	pos += o.len() as u16;
45	+	parts.push(s);
46	+	}
47	+	if op == 0x85 {
48	+	// Encoded as source, destination.
49	+	parts.swap(0, 1);
50	+	}
51	+	let text = if parts.is_empty() {
52	+	info.mnemonic.to_string()
53	+	} else {
54	+	format!("{:<5} {}", info.mnemonic, parts.join(","))
55	+	};
56	+	Disasm {
57	+	text,
58	+	size: info.size,
59	+	}
60	+	}
61	+
62	+	#[cfg(test)]
63	+	mod tests {
64	+	use super::*;
65	+	use crate::asm::assemble;
66	+
67	+	/// Disassembling and re-assembling every opcode gives the same bytes.
68	+	#[test]
69	+	fn round_trips_every_opcode() {
70	+	for op in 0..=255u8 {
71	+	if op == 0xA5 {
72	+	continue;
73	+	}
74	+	let mut code = Box::new([0u8; 0x10000]);
75	+	code[0x100] = op;
76	+	code[0x101] = 0x30;
77	+	code[0x102] = 0x40;
78	+	let d = disassemble(&code, 0x100);
79	+	let src = format!("ORG 100h\n{}", d.text);
80	+	let out = assemble(&src);
81	+	assert!(out.ok(), "{op:02X} '{}': {:?}", d.text, out.diagnostics);
82	+	let bytes: Vec<u8> = out.bytes().map(\|b\| b.1).collect();
83	+	assert_eq!(
84	+	bytes,
85	+	code[0x100..0x100 + d.size as usize],
86	+	"opcode {op:02X} '{}'",
87	+	d.text
88	+	);
89	+	}
90	+	}
91	+	}

	@@ -0,0 +1,449 @@
1	+	//! Intel 8051 simulator: CPU core, memories and on-chip peripherals.
2	+
3	+	mod cpu;
4	+	pub mod disasm;
5	+	mod periph;
6	+
7	+	use std::collections::{HashSet, VecDeque};
8	+
9	+	use crate::isa;
10	+	use crate::sfr::{self, ACC, B, DPH, DPL, IE, IP, P0, P1, P2, P3, PCON, PSW, SBUF, SP};
11	+	pub use periph::Uart;
12	+
13	+	pub const CY: u8 = 0x80;
14	+	pub const AC: u8 = 0x40;
15	+	pub const OV: u8 = 0x04;
16	+	pub const PARITY: u8 = 0x01;
17	+
18	+	#[derive(Debug, Clone, PartialEq, Eq)]
19	+	pub enum Stop {
20	+	/// Ran the requested number of instructions / cycle budget.
21	+	Budget,
22	+	Breakpoint(u16),
23	+	/// A step-over / step-out target was reached.
24	+	Target,
25	+	ReservedOpcode {
26	+	pc: u16,
27	+	opcode: u8,
28	+	},
29	+	PowerDown,
30	+	}
31	+
32	+	pub struct Sim {
33	+	pub code: Box<[u8; 0x10000]>,
34	+	/// Internal RAM. Indirect addressing reaches all 256 bytes (8052-style
35	+	/// upper 128); direct addresses 80h-FFh go to the SFRs instead.
36	+	pub iram: [u8; 256],
37	+	/// SFR space 80h-FFh, indexed by `addr - 0x80`.
38	+	pub sfr: [u8; 128],
39	+	pub xram: Box<[u8; 0x10000]>,
40	+	pub pc: u16,
41	+	/// Machine cycles since reset.
42	+	pub cycles: u64,
43	+	/// Levels driven onto the port pins from outside (1 = released/high).
44	+	/// A pin reads as `latch & external`.
45	+	pub pins: [u8; 4],
46	+	pub uart: Uart,
47	+	pub idle: bool,
48	+	pub power_down: bool,
49	+	/// Priority levels of interrupts currently in service (innermost last).
50	+	pub in_service: Vec<u8>,
51	+	/// Vector of the last interrupt taken, for the UI log.
52	+	pub last_irq: Option<u16>,
53	+	/// RETI or a write to IE/IP delays interrupt acceptance by one instruction.
54	+	irq_hold: bool,
55	+	/// Pin levels of P3 in the previous cycle, for edge detection.
56	+	prev_p3: u8,
57	+	}
58	+
59	+	impl Default for Sim {
60	+	fn default() -> Self {
61	+	Self::new()
62	+	}
63	+	}
64	+
65	+	impl Sim {
66	+	pub fn new() -> Self {
67	+	let mut s = Self {
68	+	code: Box::new([0; 0x10000]),
69	+	iram: [0; 256],
70	+	sfr: [0; 128],
71	+	xram: Box::new([0; 0x10000]),
72	+	pc: 0,
73	+	cycles: 0,
74	+	pins: [0xFF; 4],
75	+	uart: Uart::default(),
76	+	idle: false,
77	+	power_down: false,
78	+	in_service: Vec::new(),
79	+	last_irq: None,
80	+	irq_hold: false,
81	+	prev_p3: 0xFF,
82	+	};
83	+	s.reset();
84	+	s
85	+	}
86	+
87	+	/// Hardware reset: SFRs to their reset values, PC to 0. Code and XRAM
88	+	/// are kept; IRAM is cleared so runs are reproducible.
89	+	pub fn reset(&mut self) {
90	+	self.iram = [0; 256];
91	+	self.sfr = [0; 128];
92	+	for p in [P0, P1, P2, P3] {
93	+	self.set_sfr(p, 0xFF);
94	+	}
95	+	self.set_sfr(SP, 0x07);
96	+	self.pc = 0;
97	+	self.cycles = 0;
98	+	self.uart.reset();
99	+	self.idle = false;
100	+	self.power_down = false;
101	+	self.in_service.clear();
102	+	self.last_irq = None;
103	+	self.irq_hold = false;
104	+	self.prev_p3 = self.port_pins(3);
105	+	}
106	+
107	+	pub fn load_code(&mut self, bytes: impl Iterator<Item = (u16, u8)>) {
108	+	self.code.fill(0);
109	+	for (a, b) in bytes {
110	+	self.code[a as usize] = b;
111	+	}
112	+	}
113	+
114	+	// ---- Raw register access ----
115	+
116	+	pub fn sfr(&self, addr: u8) -> u8 {
117	+	self.sfr[(addr & 0x7F) as usize]
118	+	}
119	+
120	+	pub fn set_sfr(&mut self, addr: u8, v: u8) {
121	+	self.sfr[(addr & 0x7F) as usize] = v;
122	+	}
123	+
124	+	pub fn acc(&self) -> u8 {
125	+	self.sfr(ACC)
126	+	}
127	+
128	+	pub fn set_acc(&mut self, v: u8) {
129	+	self.set_sfr(ACC, v);
130	+	}
131	+
132	+	pub fn b(&self) -> u8 {
133	+	self.sfr(B)
134	+	}
135	+
136	+	pub fn psw(&self) -> u8 {
137	+	self.sfr(PSW)
138	+	}
139	+
140	+	pub fn sp(&self) -> u8 {
141	+	self.sfr(SP)
142	+	}
143	+
144	+	pub fn dptr(&self) -> u16 {
145	+	u16::from_be_bytes([self.sfr(DPH), self.sfr(DPL)])
146	+	}
147	+
148	+	pub fn set_dptr(&mut self, v: u16) {
149	+	let [h, l] = v.to_be_bytes();
150	+	self.set_sfr(DPH, h);
151	+	self.set_sfr(DPL, l);
152	+	}
153	+
154	+	pub fn flag(&self, mask: u8) -> bool {
155	+	self.psw() & mask != 0
156	+	}
157	+
158	+	pub fn set_flag(&mut self, mask: u8, on: bool) {
159	+	let p = self.psw();
160	+	self.set_sfr(PSW, if on { p \| mask } else { p & !mask });
161	+	}
162	+
163	+	pub fn bank(&self) -> u8 {
164	+	(self.psw() >> 3) & 3
165	+	}
166	+
167	+	/// IRAM address of register Rn in the active bank.
168	+	pub fn reg_addr(&self, n: u8) -> u8 {
169	+	self.bank() * 8 + n
170	+	}
171	+
172	+	pub fn reg(&self, n: u8) -> u8 {
173	+	self.iram[self.reg_addr(n) as usize]
174	+	}
175	+
176	+	/// Pin levels of port `n`: latch AND externally driven level.
177	+	pub fn port_pins(&self, n: usize) -> u8 {
178	+	self.sfr(P0 + 0x10 * n as u8) & self.pins[n]
179	+	}
180	+
181	+	// ---- Addressing modes ----
182	+
183	+	/// Reads a direct address. Ports read their pins, except for
184	+	/// read-modify-write instructions (`rmw`) which read the latch.
185	+	pub fn read_direct(&self, addr: u8, rmw: bool) -> u8 {
186	+	match addr {
187	+	0x00..=0x7F => self.iram[addr as usize],
188	+	P0 \| P1 \| P2 \| P3 if !rmw => self.port_pins(((addr - P0) >> 4) as usize),
189	+	SBUF => self.uart.sbuf_rx,
190	+	_ => self.sfr(addr),
191	+	}
192	+	}
193	+
194	+	pub fn write_direct(&mut self, addr: u8, v: u8) {
195	+	match addr {
196	+	0x00..=0x7F => self.iram[addr as usize] = v,
197	+	SBUF => self.uart_transmit(v),
198	+	IE \| IP => {
199	+	self.set_sfr(addr, v);
200	+	self.irq_hold = true;
201	+	}
202	+	PCON => {
203	+	// IDL (bit 0) and PD (bit 1) take effect immediately.
204	+	self.set_sfr(addr, v);
205	+	self.power_down \|= v & 0x02 != 0;
206	+	self.idle \|= v & 0x01 != 0;
207	+	}
208	+	_ => self.set_sfr(addr, v),
209	+	}
210	+	}
211	+
212	+	pub fn read_bit(&self, bit: u8, rmw: bool) -> bool {
213	+	let (byte, idx) = sfr::bit_location(bit);
214	+	self.read_direct(byte, rmw) & (1 << idx) != 0
215	+	}
216	+
217	+	pub fn write_bit(&mut self, bit: u8, on: bool) {
218	+	let (byte, idx) = sfr::bit_location(bit);
219	+	let v = self.read_direct(byte, true);
220	+	self.write_direct(byte, if on { v \| (1 << idx) } else { v & !(1 << idx) });
221	+	}
222	+
223	+	pub fn push(&mut self, v: u8) {
224	+	let sp = self.sp().wrapping_add(1);
225	+	self.set_sfr(SP, sp);
226	+	self.iram[sp as usize] = v;
227	+	}
228	+
229	+	pub fn pop(&mut self) -> u8 {
230	+	let sp = self.sp();
231	+	self.set_sfr(SP, sp.wrapping_sub(1));
232	+	self.iram[sp as usize]
233	+	}
234	+
235	+	pub fn push_pc(&mut self) {
236	+	let [h, l] = self.pc.to_be_bytes();
237	+	self.push(l);
238	+	self.push(h);
239	+	}
240	+
241	+	pub fn pop_pc(&mut self) {
242	+	let h = self.pop();
243	+	let l = self.pop();
244	+	self.pc = u16::from_be_bytes([h, l]);
245	+	}
246	+
247	+	// ---- Execution control ----
248	+
249	+	/// Executes one instruction (or one idle cycle), then services interrupts.
250	+	pub fn step(&mut self) -> Result<(), Stop> {
251	+	if self.power_down {
252	+	return Err(Stop::PowerDown);
253	+	}
254	+	if self.idle {
255	+	self.tick(1);
256	+	} else {
257	+	let pc = self.pc;
258	+	let opcode = self.code[pc as usize];
259	+	let Some(info) = isa::info(opcode) else {
260	+	return Err(Stop::ReservedOpcode { pc, opcode });
261	+	};
262	+	self.pc = pc.wrapping_add(1);
263	+	self.execute(opcode);
264	+	let p = self.acc().count_ones() % 2 == 1;
265	+	self.set_flag(PARITY, p);
266	+	self.tick(info.cycles as u32);
267	+	}
268	+	self.service_interrupts();
269	+	Ok(())
270	+	}
271	+
272	+	fn current_call_len(&self) -> Option<u16> {
273	+	let op = self.code[self.pc as usize];
274	+	match op {
275	+	0x12 => Some(3),
276	+	_ if op & 0x1F == 0x11 => Some(2),
277	+	_ => None,
278	+	}
279	+	}
280	+
281	+	/// Runs up to `max_steps` instructions, stopping at breakpoints.
282	+	/// `resume` ignores a breakpoint at the starting PC, so execution can
283	+	/// continue from the breakpoint it last stopped at.
284	+	pub fn run(&mut self, max_steps: u32, breakpoints: &HashSet<u16>, resume: bool) -> Stop {
285	+	for i in 0..max_steps {
286	+	if (i > 0 \|\| !resume) && !self.idle && breakpoints.contains(&self.pc) {
287	+	return Stop::Breakpoint(self.pc);
288	+	}
289	+	if let Err(s) = self.step() {
290	+	return s;
291	+	}
292	+	}
293	+	Stop::Budget
294	+	}
295	+
296	+	/// Like `step`, but executes a whole ACALL/LCALL subroutine.
297	+	pub fn step_over(&mut self, max_steps: u32, breakpoints: &HashSet<u16>) -> Stop {
298	+	match self.current_call_len() {
299	+	Some(len) => {
300	+	let target = self.pc.wrapping_add(len);
301	+	let sp = self.sp();
302	+	self.run_until(max_steps, breakpoints, \|s\| s.pc == target && s.sp() == sp)
303	+	}
304	+	None => match self.step() {
305	+	Ok(()) => Stop::Target,
306	+	Err(s) => s,
307	+	},
308	+	}
309	+	}
310	+
311	+	/// Runs until the current subroutine (or interrupt handler) returns.
312	+	pub fn step_out(&mut self, max_steps: u32, breakpoints: &HashSet<u16>) -> Stop {
313	+	let sp = self.sp();
314	+	let mut returning = false;
315	+	self.run_until_with(max_steps, breakpoints, \|s, before\| {
316	+	if before {
317	+	let op = s.code[s.pc as usize];
318	+	returning = (op == 0x22 \|\| op == 0x32) && s.sp() <= sp && !s.idle;
319	+	false
320	+	} else {
321	+	returning
322	+	}
323	+	})
324	+	}
325	+
326	+	fn run_until(
327	+	&mut self,
328	+	max_steps: u32,
329	+	bps: &HashSet<u16>,
330	+	mut done: impl FnMut(&Sim) -> bool,
331	+	) -> Stop {
332	+	self.run_until_with(max_steps, bps, \|s, before\| !before && done(s))
333	+	}
334	+
335	+	/// `done(sim, before)` is called before (`true`) and after (`false`) each step.
336	+	fn run_until_with(
337	+	&mut self,
338	+	max_steps: u32,
339	+	bps: &HashSet<u16>,
340	+	mut done: impl FnMut(&Sim, bool) -> bool,
341	+	) -> Stop {
342	+	for i in 0..max_steps {
343	+	if i > 0 && !self.idle && bps.contains(&self.pc) {
344	+	return Stop::Breakpoint(self.pc);
345	+	}
346	+	done(self, true);
347	+	if let Err(s) = self.step() {
348	+	return s;
349	+	}
350	+	if done(self, false) {
351	+	return Stop::Target;
352	+	}
353	+	}
354	+	Stop::Budget
355	+	}
356	+
357	+	/// Queue bytes for the UART receiver, as if typed on a serial terminal.
358	+	pub fn uart_send(&mut self, bytes: &[u8]) {
359	+	self.uart.rx_queue.extend(bytes.iter().copied());
360	+	}
361	+
362	+	pub fn uart_rx_pending(&self) -> &VecDeque<u8> {
363	+	&self.uart.rx_queue
364	+	}
365	+	}
366	+
367	+	#[cfg(test)]
368	+	mod example_tests {
369	+	use super::Sim;
370	+	use crate::asm::assemble;
371	+
372	+	fn load(src: &str) -> Sim {
373	+	let out = assemble(src);
374	+	assert!(out.ok(), "{:?}", out.diagnostics);
375	+	let mut s = Sim::new();
376	+	s.load_code(out.bytes());
377	+	s
378	+	}
379	+
380	+	fn steps(s: &mut Sim, n: usize) {
381	+	for _ in 0..n {
382	+	s.step().unwrap();
383	+	}
384	+	}
385	+
386	+	#[test]
387	+	fn serial_hello_greets_and_echoes() {
388	+	let mut s = load(include_str!("../../examples/serial_hello.asm"));
389	+	steps(&mut s, 60_000);
390	+	assert_eq!(
391	+	String::from_utf8_lossy(&s.uart.tx_log),
392	+	"Hello from the 8051!\r\nType something: "
393	+	);
394	+	s.uart_send(b"hi\r");
395	+	steps(&mut s, 20_000);
396	+	assert!(String::from_utf8_lossy(&s.uart.tx_log).ends_with("hi\r\n"));
397	+	}
398	+
399	+	#[test]
400	+	fn timer_irq_ticks() {
401	+	let mut s = load(include_str!("../../examples/timer_irq.asm"));
402	+	steps(&mut s, 5_000);
403	+	// ~10000 cycles at one interrupt per 1000 cycles.
404	+	assert!((3..=10).contains(&s.reg(7)), "R7 = {}", s.reg(7));
405	+	}
406	+
407	+	#[test]
408	+	fn button_counts_edges_while_idle() {
409	+	let mut s = load(include_str!("../../examples/button_int0.asm"));
410	+	steps(&mut s, 20);
411	+	assert!(s.idle);
412	+	for _ in 0..3 {
413	+	s.pins[3] &= !0x04;
414	+	steps(&mut s, 10);
415	+	s.pins[3] \|= 0x04;
416	+	steps(&mut s, 10);
417	+	}
418	+	assert_eq!(s.sfr(crate::sfr::P1), 3);
419	+	}
420	+
421	+	#[test]
422	+	fn bcd_and_lookup() {
423	+	let mut s = load(include_str!("../../examples/bcd_add.asm"));
424	+	steps(&mut s, 20);
425	+	assert_eq!((s.iram[0x31], s.iram[0x30]), (0x69, 0x12));
426	+	let mut s = load(include_str!("../../examples/lookup_movc.asm"));
427	+	steps(&mut s, 3 + 4 * 5 + 3); // setup, digits 0-3, then up to MOV P2,A
428	+	assert_eq!(s.sfr(crate::sfr::P2), 0x66); // digit 4
429	+	}
430	+	}
431	+
432	+	#[cfg(test)]
433	+	mod run_tests {
434	+	use super::{Sim, Stop};
435	+	use crate::asm::assemble;
436	+	use std::collections::HashSet;
437	+
438	+	#[test]
439	+	fn breakpoint_at_chunk_boundary_is_hit() {
440	+	let out = assemble("l: NOP\nNOP\nSJMP l");
441	+	let mut s = Sim::new();
442	+	s.load_code(out.bytes());
443	+	let bps = HashSet::from([1u16]);
444	+	assert_eq!(s.run(1, &bps, true), Stop::Budget); // stops at PC 1 by budget
445	+	assert_eq!(s.run(10, &bps, false), Stop::Breakpoint(1)); // next chunk must not skip it
446	+	assert_eq!(s.run(10, &bps, true), Stop::Breakpoint(1)); // resuming loops back to it
447	+	assert_eq!(s.pc, 1);
448	+	}
449	+	}

	@@ -0,0 +1,403 @@
1	+	//! Timers 0/1, the UART and interrupt dispatch, advanced per machine cycle.
2	+
3	+	use std::collections::VecDeque;
4	+
5	+	use super::Sim;
6	+	use crate::sfr::{IE, IP, PCON, SCON, TCON, TH0, TH1, TL0, TL1, TMOD};
7	+
8	+	// TCON bits
9	+	const TF1: u8 = 0x80;
10	+	const TR1: u8 = 0x40;
11	+	const TF0: u8 = 0x20;
12	+	const TR0: u8 = 0x10;
13	+	const IE1: u8 = 0x08;
14	+	const IT1: u8 = 0x04;
15	+	const IE0: u8 = 0x02;
16	+	const IT0: u8 = 0x01;
17	+	// SCON bits
18	+	const SM2: u8 = 0x20;
19	+	const REN: u8 = 0x10;
20	+	const RB8: u8 = 0x04;
21	+	const TI: u8 = 0x02;
22	+	const RI: u8 = 0x01;
23	+	// P3 pins
24	+	const INT0_PIN: u8 = 0x04;
25	+	const INT1_PIN: u8 = 0x08;
26	+	const T0_PIN: u8 = 0x10;
27	+	const T1_PIN: u8 = 0x20;
28	+
29	+	#[derive(Debug, Clone, Copy)]
30	+	struct Shift {
31	+	byte: u8,
32	+	/// Remaining time in the mode's unit (see `Sim::uart_units`).
33	+	remaining: u32,
34	+	}
35	+
36	+	#[derive(Debug, Default)]
37	+	pub struct Uart {
38	+	/// Everything the 8051 has transmitted.
39	+	pub tx_log: Vec<u8>,
40	+	/// Bytes waiting to be received by the 8051.
41	+	pub rx_queue: VecDeque<u8>,
42	+	/// The receive half of SBUF.
43	+	pub sbuf_rx: u8,
44	+	tx: Option<Shift>,
45	+	rx: Option<Shift>,
46	+	}
47	+
48	+	impl Uart {
49	+	/// Clears the shift registers and the TX log; queued input is kept.
50	+	pub fn reset(&mut self) {
51	+	self.tx_log.clear();
52	+	self.sbuf_rx = 0;
53	+	self.tx = None;
54	+	self.rx = None;
55	+	}
56	+
57	+	pub fn transmitting(&self) -> bool {
58	+	self.tx.is_some()
59	+	}
60	+	}
61	+
62	+	/// Interrupt sources in hardware polling order: (flag test, IE/IP bit, vector).
63	+	const SOURCES: [(u8, u16); 5] = [
64	+	(0x01, 0x03),
65	+	(0x02, 0x0B),
66	+	(0x04, 0x13),
67	+	(0x08, 0x1B),
68	+	(0x10, 0x23),
69	+	];
70	+
71	+	impl Sim {
72	+	pub(super) fn tick(&mut self, cycles: u32) {
73	+	for _ in 0..cycles {
74	+	self.cycles += 1;
75	+	let p3 = self.port_pins(3);
76	+	let fell = self.prev_p3 & !p3;
77	+	self.prev_p3 = p3;
78	+	self.external_interrupts(p3, fell);
79	+	let t1_overflows = self.timers(p3, fell);
80	+	self.uart_tick(t1_overflows);
81	+	}
82	+	}
83	+
84	+	fn external_interrupts(&mut self, p3: u8, fell: u8) {
85	+	let mut tcon = self.sfr(TCON);
86	+	for (pin, it, ie) in [(INT0_PIN, IT0, IE0), (INT1_PIN, IT1, IE1)] {
87	+	if tcon & it != 0 {
88	+	if fell & pin != 0 {
89	+	tcon \|= ie;
90	+	}
91	+	} else if p3 & pin == 0 {
92	+	tcon \|= ie;
93	+	} else {
94	+	tcon &= !ie;
95	+	}
96	+	}
97	+	self.set_sfr(TCON, tcon);
98	+	}
99	+
100	+	/// Advances both timers by one machine cycle. Returns the number of
101	+	/// timer 1 overflows (the UART baud clock in modes 1 and 3).
102	+	fn timers(&mut self, p3: u8, fell: u8) -> u32 {
103	+	let tmod = self.sfr(TMOD);
104	+	let mut tcon = self.sfr(TCON);
105	+	let t0_mode = tmod & 0x03;
106	+	let mut t1_overflows = 0;
107	+
108	+	for t in 0..2u8 {
109	+	let ctl = (tmod >> (4 * t)) & 0x0F;
110	+	let mode = ctl & 0x03;
111	+	let (tr, int_pin, count_pin) = if t == 0 {
112	+	(TR0, INT0_PIN, T0_PIN)
113	+	} else {
114	+	(TR1, INT1_PIN, T1_PIN)
115	+	};
116	+	let gate_ok = ctl & 0x08 == 0 \|\| p3 & int_pin != 0;
117	+	let running = tcon & tr != 0 && gate_ok;
118	+	let event = if ctl & 0x04 != 0 {
119	+	fell & count_pin != 0
120	+	} else {
121	+	true
122	+	};
123	+
124	+	// Timer 1 is stopped in mode 3; timer 0 mode 3 also clocks TH0 from TR1.
125	+	if t == 1 && mode == 3 {
126	+	continue;
127	+	}
128	+	let (tl_addr, th_addr) = if t == 0 { (TL0, TH0) } else { (TL1, TH1) };
129	+	if t == 0 && mode == 3 && tcon & TR1 != 0 {
130	+	let th = self.sfr(TH0).wrapping_add(1);
131	+	self.set_sfr(TH0, th);
132	+	if th == 0 {
133	+	tcon \|= TF1;
134	+	}
135	+	}
136	+	if !(running && event) {
137	+	continue;
138	+	}
139	+	let (tl, th) = (self.sfr(tl_addr), self.sfr(th_addr));
140	+	let (tl, th, overflow) = match mode {
141	+	0 => {
142	+	let low = (tl.wrapping_add(1)) & 0x1F;
143	+	let th2 = if low == 0 { th.wrapping_add(1) } else { th };
144	+	((tl & 0xE0) \| low, th2, low == 0 && th2 == 0)
145	+	}
146	+	1 => {
147	+	let v = u16::from_be_bytes([th, tl]).wrapping_add(1);
148	+	let [h, l] = v.to_be_bytes();
149	+	(l, h, v == 0)
150	+	}
151	+	2 => {
152	+	let l = tl.wrapping_add(1);
153	+	if l == 0 {
154	+	(th, th, true)
155	+	} else {
156	+	(l, th, false)
157	+	}
158	+	}
159	+	_ => {
160	+	// Timer 0 mode 3: TL0 is an 8-bit timer.
161	+	let l = tl.wrapping_add(1);
162	+	(l, th, l == 0)
163	+	}
164	+	};
165	+	self.set_sfr(tl_addr, tl);
166	+	self.set_sfr(th_addr, th);
167	+	if overflow {
168	+	if t == 1 {
169	+	t1_overflows += 1;
170	+	// With timer 0 in mode 3, TF1 belongs to TH0.
171	+	if t0_mode != 3 {
172	+	tcon \|= TF1;
173	+	}
174	+	} else {
175	+	tcon \|= TF0;
176	+	}
177	+	}
178	+	}
179	+	self.set_sfr(TCON, tcon);
180	+	t1_overflows
181	+	}
182	+
183	+	/// Frame length of the current serial mode, in the units that
184	+	/// `uart_tick` counts: machine cycles (mode 0), oscillator periods
185	+	/// (mode 2) or timer 1 overflows (modes 1 and 3).
186	+	fn uart_frame(&self) -> u32 {
187	+	let smod = self.sfr(PCON) & 0x80 != 0;
188	+	let bit = \|base: u32\| if smod { base / 2 } else { base };
189	+	match self.sfr(SCON) >> 6 {
190	+	0 => 8,
191	+	1 => 10 * bit(32),
192	+	2 => 11 * bit(64),
193	+	_ => 11 * bit(32),
194	+	}
195	+	}
196	+
197	+	pub(super) fn uart_transmit(&mut self, byte: u8) {
198	+	let remaining = self.uart_frame();
199	+	self.uart.tx = Some(Shift { byte, remaining });
200	+	}
201	+
202	+	fn uart_tick(&mut self, t1_overflows: u32) {
203	+	let mode = self.sfr(SCON) >> 6;
204	+	let units = match mode {
205	+	0 => 1,
206	+	2 => 12,
207	+	_ => t1_overflows,
208	+	};
209	+	if units == 0 {
210	+	return;
211	+	}
212	+	if let Some(tx) = &mut self.uart.tx {
213	+	tx.remaining = tx.remaining.saturating_sub(units);
214	+	if tx.remaining == 0 {
215	+	self.uart.tx_log.push(tx.byte);
216	+	self.uart.tx = None;
217	+	self.set_sfr(SCON, self.sfr(SCON) \| TI);
218	+	}
219	+	}
220	+
221	+	let scon = self.sfr(SCON);
222	+	if self.uart.rx.is_none()
223	+	&& scon & REN != 0
224	+	&& scon & RI == 0
225	+	&& let Some(byte) = self.uart.rx_queue.pop_front()
226	+	{
227	+	self.uart.rx = Some(Shift {
228	+	byte,
229	+	remaining: self.uart_frame(),
230	+	});
231	+	}
232	+	if let Some(rx) = &mut self.uart.rx {
233	+	rx.remaining = rx.remaining.saturating_sub(units);
234	+	if rx.remaining == 0 {
235	+	let byte = rx.byte;
236	+	self.uart.rx = None;
237	+	// Terminal input has no 9th data bit; in modes 1-3 RB8 gets
238	+	// the stop bit (1). With SM2 set in modes 2/3 that 9th bit
239	+	// would be 0, so the byte is discarded.
240	+	let mut scon = self.sfr(SCON);
241	+	if !(mode >= 2 && scon & SM2 != 0) {
242	+	self.uart.sbuf_rx = byte;
243	+	scon \|= RI;
244	+	if mode == 1 {
245	+	scon \|= RB8;
246	+	} else if mode >= 2 {
247	+	scon &= !RB8;
248	+	}
249	+	}
250	+	self.set_sfr(SCON, scon);
251	+	}
252	+	}
253	+	}
254	+
255	+	pub(super) fn service_interrupts(&mut self) {
256	+	if self.irq_hold {
257	+	self.irq_hold = false;
258	+	return;
259	+	}
260	+	let ie = self.sfr(IE);
261	+	if ie & 0x80 == 0 {
262	+	return;
263	+	}
264	+	let tcon = self.sfr(TCON);
265	+	let scon = self.sfr(SCON);
266	+	let pending = \|mask: u8\| match mask {
267	+	0x01 => tcon & IE0 != 0,
268	+	0x02 => tcon & TF0 != 0,
269	+	0x04 => tcon & IE1 != 0,
270	+	0x08 => tcon & TF1 != 0,
271	+	_ => scon & (RI \| TI) != 0,
272	+	};
273	+	let ip = self.sfr(IP);
274	+	let current = self.in_service.last().copied();
275	+	for level in [1u8, 0] {
276	+	if current.is_some_and(\|c\| c >= level) {
277	+	continue;
278	+	}
279	+	let found = SOURCES.iter().find(\|&&(mask, _)\| {
280	+	ie & mask != 0 && (ip & mask != 0) == (level == 1) && pending(mask)
281	+	});
282	+	if let Some(&(mask, vector)) = found {
283	+	// Hardware clears timer flags and edge-triggered external flags.
284	+	let mut tcon = self.sfr(TCON);
285	+	match mask {
286	+	0x01 if tcon & IT0 != 0 => tcon &= !IE0,
287	+	0x02 => tcon &= !TF0,
288	+	0x04 if tcon & IT1 != 0 => tcon &= !IE1,
289	+	0x08 => tcon &= !TF1,
290	+	_ => {}
291	+	}
292	+	self.set_sfr(TCON, tcon);
293	+	self.idle = false;
294	+	self.set_sfr(PCON, self.sfr(PCON) & !0x01);
295	+	self.push_pc();
296	+	self.pc = vector;
297	+	self.in_service.push(level);
298	+	self.last_irq = Some(vector);
299	+	self.tick(2);
300	+	return;
301	+	}
302	+	}
303	+	}
304	+	}
305	+
306	+	#[cfg(test)]
307	+	mod tests {
308	+	use crate::asm::assemble;
309	+	use crate::sim::Sim;
310	+
311	+	fn sim(src: &str) -> Sim {
312	+	let out = assemble(src);
313	+	assert!(out.ok(), "{:?}", out.diagnostics);
314	+	let mut s = Sim::new();
315	+	s.load_code(out.bytes());
316	+	s
317	+	}
318	+
319	+	#[test]
320	+	fn timer0_mode1_interrupt() {
321	+	let mut s = sim("
322	+	ORG 0
323	+	LJMP main
324	+	ORG 0Bh
325	+	INC R7
326	+	RETI
327	+	main: MOV TMOD,#01h
328	+	MOV TH0,#0FFh
329	+	MOV TL0,#0F0h
330	+	SETB ET0
331	+	SETB EA
332	+	SETB TR0
333	+	SJMP $
334	+	");
335	+	let mut saw_vector = false;
336	+	for _ in 0..200 {
337	+	s.step().unwrap();
338	+	saw_vector \|= s.pc == 0x0B;
339	+	}
340	+	assert!(saw_vector);
341	+	assert!(s.reg(7) >= 1);
342	+	// TF0 is cleared by hardware on vectoring.
343	+	assert_eq!(s.sfr(crate::sfr::TCON) & 0x20, 0);
344	+	}
345	+
346	+	#[test]
347	+	fn timer_mode2_auto_reload() {
348	+	let mut s = sim("MOV TMOD,#02h\nMOV TH0,#0F0h\nMOV TL0,#0FEh\nSETB TR0\nSJMP $");
349	+	for _ in 0..8 {
350	+	s.step().unwrap();
351	+	}
352	+	assert!(s.sfr(crate::sfr::TCON) & 0x20 != 0, "TF0 set");
353	+	assert!(s.sfr(crate::sfr::TL0) >= 0xF0);
354	+	}
355	+
356	+	#[test]
357	+	fn uart_tx_and_rx() {
358	+	let mut s = sim("
359	+	MOV TMOD,#20h ; timer 1 mode 2
360	+	MOV TH1,#0FDh ; 9600 baud @ 11.0592 MHz
361	+	SETB TR1
362	+	MOV SCON,#50h ; mode 1, REN
363	+	MOV SBUF,#'H'
364	+	w: JNB TI,w
365	+	CLR TI
366	+	r: JNB RI,r
367	+	MOV A,SBUF
368	+	SJMP $
369	+	");
370	+	s.uart_send(b"x");
371	+	for _ in 0..10_000 {
372	+	s.step().unwrap();
373	+	}
374	+	assert_eq!(s.uart.tx_log, b"H");
375	+	assert_eq!(s.acc(), b'x');
376	+	}
377	+
378	+	#[test]
379	+	fn external_interrupt_edge() {
380	+	let mut s = sim("
381	+	LJMP main
382	+	ORG 03h
383	+	INC R0
384	+	RETI
385	+	main: SETB IT0
386	+	SETB EX0
387	+	SETB EA
388	+	SJMP $
389	+	");
390	+	for _ in 0..10 {
391	+	s.step().unwrap();
392	+	}
393	+	s.pins[3] &= !0x04; // pull INT0 low
394	+	for _ in 0..10 {
395	+	s.step().unwrap();
396	+	}
397	+	s.pins[3] \|= 0x04;
398	+	for _ in 0..10 {
399	+	s.step().unwrap();
400	+	}
401	+	assert_eq!(s.reg(0), 1, "one falling edge, one interrupt");
402	+	}
403	+	}

	@@ -0,0 +1,68 @@
1	+	mod app;
2	+	pub mod draw;
3	+	mod syntax;
4	+
5	+	use std::io;
6	+	use std::path::PathBuf;
7	+	use std::time::{Duration, Instant};
8	+
9	+	use ratatui::crossterm::event::{
10	+	self, DisableMouseCapture, EnableMouseCapture, Event, KeyEventKind,
11	+	};
12	+	use ratatui::crossterm::execute;
13	+	use ratatui::crossterm::terminal::{
14	+	EnterAlternateScreen, LeaveAlternateScreen, disable_raw_mode, enable_raw_mode,
15	+	};
16	+
17	+	use app::App;
18	+
19	+	const FRAME: Duration = Duration::from_millis(33);
20	+
21	+	pub fn run(path: Option<PathBuf>, clock_mhz: f64) -> io::Result<()> {
22	+	let mut terminal = ratatui::init();
23	+	execute!(io::stdout(), EnableMouseCapture)?;
24	+	let mut app = App::new(path, clock_mhz);
25	+	let result = event_loop(&mut terminal, &mut app);
26	+	let _ = execute!(io::stdout(), DisableMouseCapture);
27	+	ratatui::restore();
28	+	result
29	+	}
30	+
31	+	fn event_loop(terminal: &mut ratatui::DefaultTerminal, app: &mut App) -> io::Result<()> {
32	+	let mut next_frame = Instant::now();
33	+	while !app.quit {
34	+	terminal.draw(\|f\| draw::draw(f, app))?;
35	+	// Wait for input until the next frame is due; while running, the
36	+	// simulation advances once per frame.
37	+	let timeout = next_frame.saturating_duration_since(Instant::now());
38	+	if event::poll(timeout)? {
39	+	match event::read()? {
40	+	Event::Key(k) if k.kind != KeyEventKind::Release => app.on_key(k),
41	+	Event::Mouse(m) => app.on_mouse(m),
42	+	_ => {}
43	+	}
44	+	}
45	+	if std::mem::take(&mut app.external_edit) {
46	+	suspend()?;
47	+	app.edit_externally();
48	+	resume(terminal)?;
49	+	}
50	+	if Instant::now() >= next_frame {
51	+	app.tick();
52	+	next_frame = Instant::now() + FRAME;
53	+	}
54	+	}
55	+	Ok(())
56	+	}
57	+
58	+	/// Hands the terminal back to the shell (for `$EDITOR`).
59	+	fn suspend() -> io::Result<()> {
60	+	execute!(io::stdout(), DisableMouseCapture, LeaveAlternateScreen)?;
61	+	disable_raw_mode()
62	+	}
63	+
64	+	fn resume(terminal: &mut ratatui::DefaultTerminal) -> io::Result<()> {
65	+	enable_raw_mode()?;
66	+	execute!(io::stdout(), EnterAlternateScreen, EnableMouseCapture)?;
67	+	terminal.clear()
68	+	}

	@@ -0,0 +1,122 @@
1	+	//! Minimal 8051 assembly syntax highlighting.
2	+
3	+	use ratatui::style::{Color, Modifier, Style};
4	+	use ratatui::text::Span;
5	+
6	+	use crate::{isa, sfr};
7	+
8	+	const COMMENT: Style = Style::new().fg(Color::DarkGray);
9	+	const LABEL: Style = Style::new().fg(Color::Yellow);
10	+	const MNEMONIC: Style = Style::new().fg(Color::Cyan).add_modifier(Modifier::BOLD);
11	+	const DIRECTIVE: Style = Style::new().fg(Color::Magenta);
12	+	const REGISTER: Style = Style::new().fg(Color::LightBlue);
13	+	const NUMBER: Style = Style::new().fg(Color::LightGreen);
14	+	const STRING: Style = Style::new().fg(Color::Green);
15	+	const SFR: Style = Style::new().fg(Color::LightMagenta);
16	+
17	+	fn is_directive(w: &str) -> bool {
18	+	matches!(
19	+	w,
20	+	"ORG"
21	+	\| "DB"
22	+	\| "DW"
23	+	\| "DS"
24	+	\| "END"
25	+	\| "EQU"
26	+	\| "SET"
27	+	\| "BIT"
28	+	\| "DATA"
29	+	\| "IDATA"
30	+	\| "XDATA"
31	+	\| "CODE"
32	+	\| "CSEG"
33	+	\| "XSEG"
34	+	\| "DSEG"
35	+	\| "AT"
36	+	\| "USING"
37	+	\| "NAME"
38	+	\| "BYTE"
39	+	\| "WORD"
40	+	)
41	+	}
42	+
43	+	fn word_style(w: &str, first_word: bool) -> Style {
44	+	let u = w.to_ascii_uppercase();
45	+	let reg = matches!(u.as_str(), "A" \| "AB" \| "C" \| "DPTR" \| "PC")
46	+	\|\| (u.len() == 2
47	+	&& u.starts_with('R')
48	+	&& u.as_bytes()[1].is_ascii_digit()
49	+	&& u.as_bytes()[1] < b'8');
50	+	if reg {
51	+	REGISTER
52	+	} else if is_directive(&u) {
53	+	DIRECTIVE
54	+	} else if first_word && isa::is_mnemonic(&u) {
55	+	MNEMONIC
56	+	} else if sfr::SFRS.iter().chain(sfr::BITS).any(\|(n, _)\| *n == u) {
57	+	SFR
58	+	} else if matches!(
59	+	u.as_str(),
60	+	"HIGH" \| "LOW" \| "MOD" \| "AND" \| "OR" \| "XOR" \| "NOT" \| "SHL" \| "SHR"
61	+	) {
62	+	DIRECTIVE
63	+	} else {
64	+	Style::new()
65	+	}
66	+	}
67	+
68	+	/// Splits a source line into styled spans, applying `base` underneath.
69	+	pub fn highlight(line: &str, base: Style) -> Vec<Span<'static>> {
70	+	let chars: Vec<char> = line.chars().collect();
71	+	let mut spans = Vec::new();
72	+	let mut i = 0;
73	+	let mut seen_word = false;
74	+	let push = \|spans: &mut Vec<Span<'static>>, s: String, st: Style\| {
75	+	spans.push(Span::styled(s, base.patch(st)))
76	+	};
77	+	while i < chars.len() {
78	+	let c = chars[i];
79	+	let start = i;
80	+	if c == ';' {
81	+	push(&mut spans, chars[i..].iter().collect(), COMMENT);
82	+	break;
83	+	} else if c == '\'' \|\| c == '"' {
84	+	i += 1;
85	+	while i < chars.len() && chars[i] != c {
86	+	i += 1;
87	+	}
88	+	i = (i + 1).min(chars.len());
89	+	push(&mut spans, chars[start..i].iter().collect(), STRING);
90	+	} else if c.is_ascii_alphabetic() \|\| c == '_' \|\| c == '?' {
91	+	while i < chars.len()
92	+	&& (chars[i].is_ascii_alphanumeric() \|\| chars[i] == '_' \|\| chars[i] == '?')
93	+	{
94	+	i += 1;
95	+	}
96	+	let w: String = chars[start..i].iter().collect();
97	+	let is_label = !seen_word && chars.get(i) == Some(&':');
98	+	let style = if is_label {
99	+	LABEL
100	+	} else {
101	+	let st = word_style(&w, !seen_word);
102	+	seen_word = true;
103	+	st
104	+	};
105	+	push(&mut spans, w, style);
106	+	} else if c.is_ascii_digit() \|\| c == '#' \|\| c == '$' {
107	+	i += 1;
108	+	while i < chars.len() && chars[i].is_ascii_alphanumeric() {
109	+	i += 1;
110	+	}
111	+	push(&mut spans, chars[start..i].iter().collect(), NUMBER);
112	+	} else {
113	+	while i < chars.len()
114	+	&& !(chars[i].is_ascii_alphanumeric() \|\| "_?;'\"#$".contains(chars[i]))
115	+	{
116	+	i += 1;
117	+	}
118	+	push(&mut spans, chars[start..i].iter().collect(), Style::new());
119	+	}
120	+	}
121	+	spans
122	+	}